Patents by Inventor Andreas Meiser
Andreas Meiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130240955Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Andreas Meiser
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Publication number: 20130234145Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Andreas Meiser
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Publication number: 20130230956Abstract: A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.Type: ApplicationFiled: March 25, 2013Publication date: September 5, 2013Applicant: Infineon Technologies AGInventors: Andreas Meiser, Till Schloesser, Markus Zundel
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Patent number: 8476734Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: GrantFiled: June 9, 2011Date of Patent: July 2, 2013Assignee: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20130153916Abstract: One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Joachim Weyers, Anton Mauder, Franz Hirler, Andreas Meiser, Ulrich Glaser
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Patent number: 8404557Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate having a main horizontal surface, an opposite surface and a completely embedded dielectric region. A deep vertical trench is etched from the main horizontal surface into the semiconductor substrate using the dielectric region as an etch stop. A vertical transistor structure is formed in the semiconductor substrate. A first metallization in ohmic contact with the transistor structure is formed on the main horizontal surface. The semiconductor substrate is thinned at the opposite surface at least close to the dielectric region. Further, a semiconductor device is provided.Type: GrantFiled: April 18, 2011Date of Patent: March 26, 2013Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Andreas Meiser
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Patent number: 8373449Abstract: A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.Type: GrantFiled: December 30, 2010Date of Patent: February 12, 2013Assignee: Infineon Technologies AGInventors: Steffen Thiele, Andreas Meiser
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Publication number: 20130005099Abstract: A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.Type: ApplicationFiled: June 29, 2012Publication date: January 3, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Hans Weber, Franz Hirler, Andreas Meiser, Anton Mauder, Kurt Sorschag, Stefan Gamerith, Roman Knoefler
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Publication number: 20120289003Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.Type: ApplicationFiled: July 12, 2012Publication date: November 15, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Andreas Meiser
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Publication number: 20120169377Abstract: A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: Infineon Technologies AGInventors: Steffen Thiele, Andreas Meiser
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Publication number: 20120107452Abstract: This invention relates to an aeration system comprising an aeration section, a degassing section and optionally an additional section. This invention also relates to a horizontal photobioreactor comprising the aeration system. This invention further relates to methods of using the photobioreactors.Type: ApplicationFiled: April 16, 2010Publication date: May 3, 2012Inventors: Andreas Meiser, Lawrence A. Walmsley
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Publication number: 20110256688Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: ApplicationFiled: June 9, 2011Publication date: October 20, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20110233721Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Patent number: 7982284Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: GrantFiled: June 28, 2006Date of Patent: July 19, 2011Assignee: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20110124087Abstract: A method of operating a closed photobioreactor for cultivation of phototrophic microorganisms. The photobioreactor comprises a culture liquid and is partially or completely surrounded by water of a water body. A density difference between the culture liquid and the surrounding water is provided so that the position of the photobioreactor in the water body is controlled. A closed photobioreactor for cultivation of phototrophic microorganisms. The photobioreactor is adapted to comprise a culture liquid and to be partially or completely surrounded by water of a water body. The photobioreactor comprises means for determining the density difference between the culture liquid and the surrounding water.Type: ApplicationFiled: January 19, 2009Publication date: May 26, 2011Applicant: Aveston Grifford Ltd.Inventors: Andreas Meiser, Miguel Verhein
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Patent number: 7804135Abstract: An integrated semiconductor diode arrangement is provided. The arrangement includes an anode region and a cathode region that are formed in a semiconductor material region. The anode region has an arrangement of alternately occurring and directly adjacent first and second anode zones, which alternate in their conductivity type. The anode region furthermore has a first particular anode zone of the second conductivity type, the lateral extent of which is comparatively larger than that of the further anode zones of the same conductivity type.Type: GrantFiled: January 25, 2005Date of Patent: September 28, 2010Assignee: Infineon Technologies AGInventors: Nils Jensen, Andreas Meiser
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Patent number: 7470396Abstract: A device for establishing an isolated perfusion including a pump arrangement, a venous catheter, and an arterial catheter, for establishing an artificial circulation in a target area of a human or animal body, which artificial circulation is isolated from the systemic circulation. The device has first means for feeding an analysis gas into the artificial circulation, and second means for monitoring whether a blood exchange takes place between the artificial circulation and the systemic circulation.Type: GrantFiled: September 25, 2003Date of Patent: December 30, 2008Assignee: Jostra AGInventors: Andreas Meiser, Achim Mumme
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Patent number: 7468307Abstract: A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.Type: GrantFiled: June 28, 2006Date of Patent: December 23, 2008Assignee: Infineon Technologies AGInventors: Walter Hartner, Andreas Meiser, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20080012090Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: ApplicationFiled: June 28, 2006Publication date: January 17, 2008Inventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20070018195Abstract: A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.Type: ApplicationFiled: June 28, 2006Publication date: January 25, 2007Inventors: Walter Hartner, Andreas Meiser, Hermann Gruber, Dietrich Bonart, Thomas Gross