Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: A signal processing device including a first signal processing chain having a first output signal; a second signal processing chain comprising a second output signal with a higher accuracy than the first output signal; a controller configured to switch, based on a desired accuracy, whether to switch between the first and second signal processing chains as a path for an original input signal; and a modifier configured to modify the original input signal, the first output signal, or the second output signal to generate a modified input, a modified first output, or a modified second output signal when the controller switches between the first and second signal processing chains.

Abstract: In a method for determining an interpolated complex valued sample, a radial component of the interpolated sample is determined using information on a radial component and information on of a phase component of a first complex valued sample and of a second complex valued sample.

Abstract: A radio frequency signal synthesizer circuit includes a digital to analog converter configured to generate an analog output signal for each clock cycle of a clock signal to provide the radio frequency signal and a controlled oscillator to generate the clock signal. The controlled oscillator is configured to vary a cycle time of the clock signal for a radio frequency signal in a first frequency range in a first operation mode or to maintain a constant cycle time for a radio frequency signal in a second frequency range in a second operation mode, the second frequency range being different than the first frequency range.

Abstract: A communication device is described comprising a first transceiver chain set to communicate signals in a first frequency range, a second transceiver chain set to communicate signals in a second frequency range or set to no communication and a controller, configured to receive an instruction for a resetting of carrier aggregation comprising a setting of the first transceiver chain or the second transceiver chain to receive signals in a third frequency range different from the first frequency range and the second frequency range, to control, in response of the reception of the instruction, the second transceiver chain to receive signals within the first frequency range simultaneously with the first transceiver chain and to control the first transceiver chain, when the communication of signals within the first frequency range by the second transceiver chain fulfills a predetermined criterion, to stop communication of signals within the first frequency range.

Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Abstract: Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

Abstract: Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.

Abstract: A circuit for generating a radio frequency signal includes an amplifier configured to provide a radio frequency signal, the radio frequency signal being based on a baseband signal and a power supply configured to provide a variable supply voltage to the amplifier. A predistortion circuit is configured to modify the baseband signal; and a control circuit configured to control an operation mode of the predistortion circuit depending on a bandwidth of a radius of the baseband signal.

Abstract: A quantization circuit includes a quantizer configured to provide a quantized sample using an input quantity and an error estimator configured to determine a quantization error of the quantized sample. An error corrector is configured to correct the quantized sample by a correction value depending on the quantization error.

Abstract: A circuit for generating a radio frequency signal includes an amplifier configured to provide a radio frequency signal, the radio frequency signal being based on a baseband signal and a power supply configured to provide a variable supply voltage to the amplifier. A predistortion circuit is configured to modify the baseband signal; and a control circuit configured to control an operation mode of the predistortion circuit depending on a bandwidth of a radius of the baseband signal.

Abstract: A method and an apparatus are described which determine at least one output value based on at least one input value. The input value is provided to a processing unit, wherein a combination of intermediate values is iteratively calculated. Each intermediate value is calculated during an iteration such that the intermediate value for each iteration is buffered, using a buffer storage. Based on the combination of the buffered intermediate values a storage is accessed, the storage storing a plurality of first output values, each first output value associated with a respective combination of the buffered intermediate values, so that the first output value is output.

Abstract: An n-order noise shaper has an order n?3, wherein a first set of polynomial coefficients are optimized with respect to a useful band and wherein a second set of polynomial coefficients are optimized with respect to an optimization aim depending on an overall out of band noise and/or on a maximum out of band noise.

Abstract: A communication device is described comprising a first transceiver chain set to communicate signals in a first frequency range, a second transceiver chain set to communicate signals in a second frequency range or set to no communication and a controller, configured to receive an instruction for a resetting of carrier aggregation comprising a setting of the first transceiver chain or the second transceiver chain to receive signals in a third frequency range different from the first frequency range and the second frequency range, to control, in response of the reception of the instruction, the second transceiver chain to receive signals within the first frequency range simultaneously with the first transceiver chain and to control the first transceiver chain, when the communication of signals within the first frequency range by the second transceiver chain fulfills a predetermined criterion, to stop communication of signals within the first frequency range.

Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Abstract: Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: In a method for determining an interpolated complex valued sample, a radial component of the interpolated sample is determined using information on a radial component and information on of a phase component of a first complex valued sample and of a second complex valued sample.

Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.