Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

Abstract: A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: A filter having an impulse response including a first partial impulse response and a second partial impulse response includes a supplementary filter having a supplementary impulse response. A first filter has the first partial impulse response using an output of the supplementary filter as an input and a second filter has the second partial impulse response using an output of the supplementary filter as an input.

Abstract: A quantization circuit includes a quantizer configured to provide a quantized sample using an input quantity and an error estimator configured to determine a quantization error of the quantized sample. An error corrector is configured to correct the quantized sample by a correction value depending on the quantization error.

Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Abstract: A device includes a digital-to-time converter and an interpolator having a data input and a data output coupled to the digital-to-time converter. The interpolator may be configured to receive a converter control signal at the data input and to provide an interpolated converter control signal at the data output. An interpolation rate of the interpolator may depend on the converter control signal.

Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Abstract: An apparatus includes a digital processing unit configured to process input signals comprising a variable number of data frequency bands. The digital processing unit is configured to set its processing frequency range for processing the input signal based on the number of data frequency bands in the input signal to be processed. Other embodiments are also disclosed.

Abstract: An n-order noise shaper has an order n?3, wherein a first set of polynomial coefficients are optimized with respect to a useful band and wherein a second set of polynomial coefficients are optimized with respect to an optimization aim depending on an overall out of band noise and/or on a maximum out of band noise.

Abstract: A method and an apparatus for modifying a complex-valued signal are described, the complex-valued signal representing a first symbol and a second symbol. A signal trajectory of the complex-valued signal between the first and second symbols is determined, and, if the signal trajectory passes nearby the constellation origin, the signal trajectory is altered to run closer to the constellation origin.

Abstract: In order to reduce the area and power consumption of MAC units, some aspects of the present disclosure relate to MAC units having a feedback path with an arithmetic element disposed thereon. The arithmetic element is often controlled so as to limit the number of bits needed in the data path, thereby limiting power and area required for the MAC unit.

Abstract: A method and an apparatus for modifying a complex-valued signal are described, the complex-valued signal representing a first symbol and a second symbol. A signal trajectory of the complex-valued signal between the first and second symbols is determined, and, if the signal trajectory passes nearby the constellation origin, the signal trajectory is altered to run closer to the constellation origin.

Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.

Abstract: A device for reducing an error signal component of a transmit signal in a receive signal, including an interface, a transmit signal generator, a transmitting/receiving device, a correction signal generator and a combiner. The combiner is configured to combine the receive signal with a correction signal from the correction signal generator in order to reduce the proportion that is based on the known wideband error signal component of the transmit signal in the receive signal.

Abstract: A method and an apparatus are described which determine at least one output value based on at least one input value. The input value is provided to a processing unit, wherein a combination of intermediate values is iteratively calculated. Each intermediate value is calculated during an iteration such that the intermediate value for each iteration is buffered, using a buffer storage. Based on the combination of the buffered intermediate values a storage is accessed, the storage storing a plurality of first output values, each first output value associated with a respective combination of the buffered intermediate values, so that the first output value is output.

Abstract: A method for modifying a characteristic of a representation of a complex-valued signal which comprises at least a representation of a first and a second complex-valued symbol comprising deriving a relative phase angle between the representation of the first and the second complex-valued symbols. The method further comprises combining a representation of a complex-valued enhancement pulse and the representation of the complex-valued signal to obtain a representation of a first and a second corrected complex-valued symbol, wherein the enhancement pulse is chosen such that the relative phase angle between the first and second corrected symbols is smaller than a predetermined threshold.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: An apparatus includes a digital processing unit configured to process input signals comprising a variable number of data frequency bands. The digital processing unit is configured to set its processing frequency range for processing the input signal based on the number of data frequency bands in the input signal to be processed. Other embodiments are also disclosed.

Abstract: An apparatus comprises a filter unit comprising a plurality of different filters each configured to filter a first signal when selected. The apparatus may further comprise a control unit configured to select one of the plurality of filters depending on a strength of the first signal. Related methods may also be performed.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.