Abstract: Carrier phase detector for calculation of a feedback signal (D) for a carrier phase loop in a receiver, which loop detects a phase error (??) between a phase (?in) of a received signal (Ein), which comprises a sequence of received data symbols, and a nominal phase (?nom) of a nominal data symbol (Enom), with the carrier phase detector in each case calculating the feedback signal (D) as a function of the real part and of the imaginary part of a received data symbol (Ein) , with a received data symbol (Ein) whose phase is in a boundary phase area being weighted gradually to a lesser extent during the calculation of the feedback signal (D), with the boundary phase area in each case being arranged symmetrically with respect to a mid-phase (?mid) which is located in the centre between the two nominal phases (?nom) of equidistant nominal data symbols (Enom), and having a phase extent which is determined by a boundary phase (?g).

Abstract: The invention features a filter arrangement for filtering an input signal that includes a transmitter signal having a predetermined pulse shape at a receiving end to transmit the input signal, a decimation filter to decimate the input signal that includes a passband frequency range and a wide transition frequency range with an amplitude attenuation, and a matching filter to match the input signal to the pulse shape of the transmitter signal. Such filter arrangements also feature passband frequency ranges for decimation filters which are smaller than the ranges for matching filters.

Abstract: Apparatus for filtering data symbols (ES) for a decision based data processing system (7) having a buffer store (13) for buffer-storing a sequence of n sequentially received data symbols (ES) and having an nth-order median filter (24) which calculates the minimum intervals (amin) between the n buffer-stored data symbols and nominal data symbols (ESnominal) and filters out that data symbol whose calculated minimum interval (aImin) has a mean value for the calculated minimum intervals.

Abstract: The channel estimates for the subcarriers are used to determine the signal strength distribution in the form of a cumulative histogram. The latter is used to determine, as a signal strength threshold value E, that maximum signal strength whose magnitude is less than or equal to the signal strengths of a predetermined number L of subcarriers which are to be limited, i.e. saturated, in the signal processing path. The signal strength threshold value E and a constant K are used to form a multiplication factor M with which the data signals are weighted or by which the data signals are multiplied, the L subcarriers being limited to a fixed value after multiplication.

Abstract: Digital filter for filtering a digital input signal with a variable filter length (l), it being possible to switch over the filter length (l) of the digital filter (8) as a function of a variable input clock frequency (fin) of the digital input signal without the ratio between the input clock frequency (fin) and an output clock frequency (fout) of the filtered digital output signal which is output by the digital filter (8) changing.

Abstract: A mixer for mixing a digital input signal with a sampled sinusoidal signal, comprising a calculating circuit for calculating multipliers (MC) of a multiplier group (MG) which exhibits a number of dividing circuits for dividing the digital input signal applied to an input of the mixer, and a number of switchable adders/subtractors, the dividing factors of the dividing circuits being Horner coefficients of the resolved multipliers (MC) of the multiplier group (MG), the adders/subtractors being controlled in dependence on a first control bit (SUB/ADD) read out of a memory; a demultiplexer for switching through a zero value or the multiplier (MC) calculated by the calculating circuit in dependence on a second control bit (zero) read out of the memory; and comprising a sign circuit for outputting the positive or negative value switched through by the demultiplexer to an output of the mixer in dependence on a third control bit (SIGN) read out of the memory.

Abstract: An analog-to-digital converter circuit including an analog-to-digital converter and calibrating circuit, preferably in the form of a digital logic, for the auto-calibration of the analog-to-digital converter. This configuration produces a very high quality analog-to-digital converter with a very low surface area requirement. The calibrating circuit corrects any errors of the analog-to-digital converter outside or inside of the analog-to-digital converter.

Abstract: QAM receiver with integrated measuring circuit for measuring the power density of a received signal, the QAM receiver being switchable between a test mode of operation and a receive mode of operation.

Abstract: Receiver for receiving a received signal with a carrier frequency loop (18) which generates a carrier frequency deviation detection signal (TF) for detecting a carrier frequency of the received signal in a first carrier frequency capture range; a carrier phase loop (32) which generates a carrier phase deviation detection signal (TP) for detecting a carrier phase of the received signal, and settles when the carrier frequency deviation detection signal (TF) is within a second carrier frequency capture range; and with an offset control circuit (29) which changes the carrier frequency deviation detection signal (TF) and/or changes the second carrier frequency capture range by means of an offset control signal until a carrier phase lock detection circuit (21) indicates to the offset control circuit that the carrier phase offset of the received signal is less than an adjustable threshold value.

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: An analog-to-digital converter circuit including an analog-to-digital converter and calibrating circuit, preferably in the form of a digital logic, for the auto-calibration of the analog-to-digital converter. This configuration produces a very high quality analog-to-digital converter with a very low surface area requirement. The calibrating circuit corrects any errors of the analog-to-digital converter outside or inside of the analog-to-digital converter.

Abstract: An analogue frontend, such as is used, for example, in receivers for communications equipment, comprises a plurality of analogue components (1-3) which are connected upstream of an analogue/digital converter (4). In order to control the drive level of the individual analogue components (1-3) precisely, the input of the analogue/digital converter (4) can optionally be connected via a switch-over device (8) to the output of any one of the analogue components (1-3) and a drive level control signal for the respective analogue component (1-3) can be generated by a digital control device (5) by evaluating the sampled value which is then supplied by the analogue/digital converter (4).

Abstract: Receiver having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling instants of a reception signal which is transmitted from a transmitter (2) with a transmission filter via a transmission channel (3) to the receiver (1), having

Abstract: The invention relates to an interpolation filter and to a method for filtering a digital input signal. The interpolation filter has an amplitude characteristic with a low-pass-shaped damping curve in the useful signal frequency range of the digital input signal. The group delay time of the interpolation filter is essentially constant in the useful signal frequency range and can be adjusted within a clock period of the equidistant digital signal.

Abstract: Digital filter for filtering a digital input signal with a variable filter length (1), it being possible to switch over the filter length (1) of the digital filter (8) as a function of a variable input clock frequency (fin) of the digital input signal without the ratio between the input clock frequency (fin) and an output clock frequency (fout) of the filtered digital output signal which is output by the digital filter (8) changing.

Abstract: The invention relates to a method for encrypting or decrypting a sequence of successive data words in a data communications device, the method comprising executing an algorithm in which a sequence of quasi-random encryption words is generated from predetermined start values by performing operations in a finite group, and in which a respective one of the encryption words is combined with a respective one of the data words.

Abstract: An analogue frontend, such as is used, for example, in receivers for communications equipment, comprises a plurality of analogue components (1-3) which are connected upstream of an analogue/digital converter (4). In order to control the drive level of the individual analogue components (1-3) precisely, the input of the analogue/digital converter (4) can optionally be connected via a switch-over device (8) to the output of any one of the analogue components (1-3) and a drive level control signal for the respective analogue component (1-3) can be generated by a digital control device (5) by evaluating the sampled value which is then supplied by the analogue/digital converter (4).

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: A facility for reducing the data rate of a data sequence (d1) is provided, including a switchable filter device (1) which delivers first output values (dn) after a sampling intervals in a first state and second output values (dm) after a +1 sampling intervals in a second state, and which has at least one tracking data window (dw) of different sizes (dwf1, dwf2) for forming filtered data values (df'). A control device (10) causes n first output values (dn) and m second output values (dm) to be formed within equally long time periods (I2) of the data sequence (d1), with the number of n first and m second output values being determined by a rule r=a+m/(n+m), where r is a desired data rate reduction factor.

Abstract: A filter combination for sampling rate conversion is disclosed comprising a series combination of: an input low-pass filter (1) whose attenuation characteristic (tp1) has at least one first attenuation value (a1) in the vicinity of one-half and 1.5 times the frequency of a digitization clock (f1); a time-invariant interpolation filter (2) for increasing the number of samples from that of the first data sequence (d1) by an integral factor whose attenuation characteristic (tp2) has at least one second attenuation value (a2) in the vicinity of the frequency of the digitization clock (f1) and essentially at least one third attenuation value (a3) in the region between one-half and 1.