Abstract: The invention relates to a weighting circuit for a receiver (1), which is designed to receive a multi-carrier signal consisting of carrier signals. According to the invention, the carrier signals are weighted by the weighting circuit (18) in such a way that the parasitic signal energy has the same intensity in all weighted carrier signals. In a preferred embodiment of the invention, the weighting circuit comprises at least one multiplier that multiplies an assigned a carrier signal by a stored weighting co-efficient. The stored weighting coefficients constitute reliability information for the various carrier signals.

Abstract: A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: The invention relates to a method for compensation for any phase and/or amplitude error in a receiver having a complex processing branch and a complex-conjugate processing branch, wherein an error-compensated complex signal component is determined by subtraction of a complex-conjugate signal component and to which a correction parameter is applied, from a complex signal component. The correction parameter is determined on the basis of a function of a quotient of the complex signal component and the complex-conjugate signal component.

Abstract: In order to reduce the area and power consumption of MAC units, some aspects of the present disclosure relate to MAC units having a feedback path with an arithmetic element disposed thereon. The arithmetic element is often controlled so as to limit the number of bits needed in the data path, thereby limiting power and area required for the MAC unit.

Abstract: A device includes a digital-to-time converter and an interpolator having a data input and a data output coupled to the digital-to-time converter. The interpolator may be configured to receive a converter control signal at the data input and to provide an interpolated converter control signal at the data output. An interpolation rate of the interpolator may depend on the converter control signal.

Abstract: A device for reducing an error signal component of a transmit signal in a receive signal, including an interface, a transmit signal generator, a transmitting/receiving device, a correction signal generator and a combiner. The combiner is configured to combine the receive signal with a correction signal from the correction signal generator in order to reduce the proportion that is based on the known wideband error signal component of the transmit signal in the receive signal.

Abstract: A system having a filter is disclosed. One embodiment includes at least two polyphase filter branches, each of the polyphase filter branches including a respective recursive allpass filter, wherein the filter approximates a linear filter.

Abstract: A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide an interpolated oscillator control signal at the data output. An interpolation rate of the interpolator may depend on the oscillator control signal. Alternatively, a device can include a digitally controlled oscillator having a control input, a sampling unit coupled to the control input of the digitally controlled oscillator, and a timing error detector coupled to an output of the digitally controlled oscillator. The sampling rate of the sampling unit can depend on an output of the timing error detector.

Abstract: A method for modifying a characteristic of a representation of a complex-valued signal which comprises at least a representation of a first and a second complex-valued symbol comprising deriving a relative phase angle between the representation of the first and the second complex-valued symbols. The method further comprises combining a representation of a complex-valued enhancement pulse and the representation of the complex-valued signal to obtain a representation of a first and a second corrected complex-valued symbol, wherein the enhancement pulse is chosen such that the relative phase angle between the first and second corrected symbols is smaller than a predetermined threshold.

Abstract: A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Abstract: Some embodiments discussed relate to an apparatus and method for processing signals, comprising receiving an input signal and forming a stream of digital samples of the input signal by sampling at a sampling frequency and mixing the stream of digital samples using a mixer sequence having a sine sequence and a cosine sequence based on the sampling frequency to generate an input sequence, each of the sine sequence and the cosine sequence including a plurality of components in an arrangement such that at least one of the components has a zero value and the remaining components has a non-zero value, and filtering the input sequence using a plurality of polyphase filter parts, each corresponding to the non-zero components of the sine sequence and the cosine sequence, and selectively combining the outputs of the polyphase filter parts to generate an in-phase sequence and a quadrature sequence.

Abstract: The channel estimates for the subcarriers are used to determine the signal strength distribution in the form of a cumulative histogram. The latter is used to determine, as a signal strength threshold value E, that maximum signal strength whose magnitude is less than or equal to the signal strengths of a predetermined number L of subcarriers which are to be limited, i.e. saturated, in the signal processing path. The signal strength threshold value E and a constant K are used to form a multiplication factor M with which the data signals are weighted or by which the data signals are multiplied, the L subcarriers being limited to a fixed value after multiplication.

Abstract: The structure of a digital filter is provided through exponentiation of a polyphase digital filter. This exponentiation may be accomplished by determining an expression for the polyphase digital filter in terms of its polyphase components, and raising the expression for the polyphase digital filter to a power. The polyphase components are then arranged in a structure based on this exponentiated expression.

Abstract: Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide an interpolated oscillator control signal at the data output. An interpolation rate of the interpolator may depend on the oscillator control signal. Alternatively, a device can include a digitally controlled oscillator having a control input, a sampling unit coupled to the control input of the digitally controlled oscillator, and a timing error detector coupled to an output of the digitally controlled oscillator. The sampling rate of the sampling unit can depend on an output of the timing error detector.

Abstract: A detector for a receiver generates a clock phase detection signal and a carrier phase detection signal from of a plurality of clock polyphase signals of an oversampled signal. The detector comprises a plurality of carrier phase detectors, a plurality of variance estimation units, a selection unit and an output unit. Each phase detector determines the carrier phase of a clock polyphase signal and emits a carrier phase signal corresponding to the carrier phase. Each variance estimation unit determines the variance of one of the carrier phase signals. The selection unit compares the variances of the carrier phase signals with one another and emits a selection signal as the clock phase detection signal for selection of that clock polyphase signal whose associated carrier phase has the smallest variance. The output unit emits at least one of the carrier phase signal as the carrier phase detection signal.

Abstract: An apparatus comprises a filter unit comprising a plurality of different filters each configured to filter a first signal when selected. The apparatus may further comprise a control unit configured to select one of the plurality of filters depending on a strength of the first signal. Related methods may also be performed.

Abstract: Carrier phase detector for calculation of a feedback signal (D) for a carrier phase loop in a receiver, which loop detects a phase error (??) between a phase (?in) of a received signal (Ein), which comprises a sequence of received data symbols, and a nominal phase (?nom) of a nominal data symbol (Enom), with the carrier phase detector in each case calculating the feedback signal (D) as a function of the real part and of the imaginary part of a received data symbol (Ein) , with a received data symbol (Ein) whose phase is in a boundary phase area being weighted gradually to a lesser extent during the calculation of the feedback signal (D), with the boundary phase area in each case being arranged symmetrically with respect to a mid-phase (?mid) which is located in the centre between the two nominal phases (?nom) of equidistant nominal data symbols (Enom), and having a phase extent which is determined by a boundary phase (?g).