Abstract: For a weighting circuit for adjusting a feedback control loop to an input signal of the feedback control loop the feedback control loop comprises a system under control and a device for generating a control difference signal by subtracting a weighted feedback signal from the input signal. The control difference signal is fed to the system under control which generates an output signal. The output signal is multiplied, by means of a weighting circuit by a sequence of multiplication factors for generating the weighted feedback signal. A frequency bandwidth of the feedback control loop is reduced step by step by the sequence of multiplication factors.

Abstract: A mixer for mixing a digital input signal with a sampled sinusoidal signal, comprising a calculating circuit for calculating multipliers (MC) of a multiplier group (MG) which exhibits a number of dividing circuits for dividing the digital input signal applied to an input of the mixer, and a number of switchable adders/subtractors, the dividing factors of the dividing circuits being Homer coefficients of the resolved multipliers (MC) of the multiplier group (MG), the adders/subtractors being controlled in dependence on a first control bit (SUB/ADD) read out of a memory; a demultiplexer for switching through a zero value or the multiplier (MC) calculated by the calculating circuit in dependence on a second control bit (zero) read out of the memory; and comprising a sign circuit for outputting the positive or negative value switched through by the demultiplexer to an output of the mixer in dependence on a third control bit (SIGN) read out of the memory.

Abstract: An apparatus is disclosed for filtering data symbols for a decision based data processing system. The apparatus includes a buffer store for buffer-storing a sequence of n sequentially received data symbols. The apparatus also includes an nth-order median filter which calculates the minimum intervals between the n buffer-stored data symbols and nominal data symbols and filters out that data symbol whose calculated minimum interval has a mean value for the calculated minimum intervals.

Abstract: A system having a filter is disclosed. One embodiment includes at least two polyphase filter branches, each of the polyphase filter branches including a respective recursive allpass filter, wherein the filter approximates a linear filter.

Abstract: Some embodiments discussed relate to an apparatus and method for processing signals, comprising receiving an input signal and forming a stream of digital samples of the input signal by sampling at a sampling frequency and mixing the stream of digital samples using a mixer sequence having a sine sequence and a cosine sequence based on the sampling frequency to generate an input sequence, each of the sine sequence and the cosine sequence including a plurality of components in an arrangement such that at least one of the components has a zero value and the remaining components has a non-zero value, and filtering the input sequence using a plurality of polyphase filter parts, each corresponding to the non-zero components of the sine sequence and the cosine sequence, and selectively combining the outputs of the polyphase filter parts to generate an in-phase sequence and a quadrature sequence.

Abstract: A digital filter combination for interpolating primary sample values of a sampled signal using an mth-order discrete-time filter and a kth-order continuous time interpolation filter, with m?3 and k?2, wherein the discrete-time filter forms n secondary sample values from at least m+1 primary sample values at equal time intervals, with n?m, and the continuous-time interpolation filter forms from at least part of the n secondary sample values an interpolated value whose temporal position with respect to that of the primary sample values is predeterminable by a normalized interpolating instant dp=tin/T, where tin is the absolute interpolating instant, and T is the period of the primary sampling rate.

Abstract: The structure of a digital filter is provided through exponentiation of a polyphase digital filter. This exponentiation may be accomplished by determining an expression for the polyphase digital filter in terms of its polyphase components, and raising the expression for the polyphase digital filter to a power. The polyphase components are then arranged in a structure based on this exponentiated expression.

Abstract: The invention relates to a method for compensation for any phase and/or amplitude error in a receiver having a complex processing branch and a complex-conjugate processing branch, wherein an error-compensated complex signal component is determined by subtraction of a complex-conjugate signal component and to which a correction parameter is applied, from a complex signal component. The correction parameter is determined on the basis of a function of a quotient of the complex signal component and the complex-conjugate signal component.

Abstract: A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Abstract: A feedback control loop having a filter response and a cut-off frequency comprises a system under control for generating an output signal being an output signal of the feedback control loop in response to a control difference signal, a loop filter for generating a feedback signal in response to the output signal and a subtraction device for generating the control difference signal by subtracting the feedback signal from an input signal fed to the feedback control loop. The loop filter is adjustable by means of a filter coefficient set having in each case at least one filter coefficient, each depending on a setting parameter, so that a filter coefficient set for adjusting the filter response of the feedback control loop can be selected and the cut-off frequency of the feedback control loop is adjustable externally in a manner dependent on the setting parameter.

Abstract: The invention improves the control behavior of a control circuit for digital signals which is used in AGCs (automatic gain control), using a simple supplementary circuit. In a first example of an embodiment, the output signal of an integrator member is looped back to the input of said integrator member in the loop-back branch of the control circuit. In a second example, a counter is provided. Said counter monitors the overflow of the integrator member and weights the input signal accordingly.

Abstract: A QAM receiver is disclosed. According to one aspect, a QAM receiver includes a signal input for receiving an analog input signal. Further, the QAM receiver includes an anti-aliasing filter and a series connected analog/digital converter for converting the received analog input signal into a digital signal. A carrier freguency loon detects a carrier freguency of the received analog input signal. A clock phase loon detects a clock phase of the received analog input signal. A control circuit is switchable between a receive mode of operation and a test mode of operation. In the test mode, the control circuit applies a center freauency adiusting signal to the carrier freauency loon for adiustment of a center freguency and applies a freguency band adjusting signal to the clock phase loon for adiustment of a freguency bandwidth to measure power level values for the entire freauency band of the received analog input signal.

Abstract: The invention relates to an interpolation filter and to a method for filtering a digital input signal. The interpolation filter has an amplitude characteristic with a low-pass-shaped damping curve in the useful signal frequency range of the digital input signal. The group delay time of the interpolation filter is essentially constant in the useful signal frequency range and can be adjusted within a clock period of the equidistant digital signal.

Abstract: Receiver is provided having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling instants of a reception signal which is transmitted from a transmitter (2) with a transmission filter via a transmission channel (3) to the receiver (1). The receiver has at least one matched filter (8) and at least one frequency matched filter (9). The magnitude of a first convolution product of the impulse response of the transmission filter, of the transmission channel (3) and of the matched filter (8), for the maximization of the signal/noise power ratio (SNR) of the reception signal, is maximal at the desired sampling instants.

Abstract: The invention relates to a weighting circuit for a receiver (1), which is designed to receive a multi-carrier signal consisting of carrier signals. According to the invention, the carrier signals are weighted by the weighting circuit (18) in such a way that the parasitic signal energy has the same intensity in all weighted carrier signals. In a preferred embodiment of the invention, the weighting circuit comprises at least one multiplier that multiplies an assigned a carrier signal by a stored weighting co-efficient. The stored weighting coefficients constitute reliability information for the various carrier signals.

Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.

Abstract: Receiver for receiving a received signal with a carrier frequency loop (18) which generates a carrier frequency deviation detection signal (TF) for detecting a carrier frequency of the received signal in a first carrier frequency capture range; a carrier phase loop (32) which generates a carrier phase deviation detection signal (TP) for detecting a carrier phase of the received signal, and settles when the carrier frequency deviation detection signal (TF) is within a second carrier frequency capture range; and with an offset control circuit (29) which changes the carrier frequency deviation detection signal (TF) and/or changes the second carrier frequency capture range by means of an offset control signal until a carrier phase lock detection circuit (21) indicates to the offset control circuit that the carrier phase offset of the received signal is less than an adjustable threshold value.

Abstract: For a weighting circuit for adjusting a feedback control loop to an input signal of the feedback control loop the feedback control loop comprises a system under control and a device for generating a control difference signal by subtracting a weighted feedback signal from the input signal. The control difference signal is fed to the system under control which generates an output signal. The output signal is multiplied, by means of a weighting circuit by a sequence of multiplication factors for generating the weighted feedback signal. A frequency bandwidth of the feedback control loop is reduced step by step by the sequence of multiplication factors.

Abstract: A feedback control loop having a filter response and a cut-off frequency comprises a system under control for generating an output signal being an output signal of the feedback control loop in response to a control difference signal, a loop filter for generating a feedback signal in response to the output signal and a subtraction device for generating the control difference signal by subtracting the feedback signal from an input signal fed to the feedback control loop. The loop filter is adjustable by means of a filter coefficient set having in each case at least one filter coefficient, each depending on a setting parameter, so that a filter coefficient set for adjusting the filter response of the feedback control loop can be selected and the cut-off frequency of the feedback control loop is adjustable externally in a manner dependent on the setting parameter.

Abstract: A detector for a receiver generates a clock phase detection signal and a carrier phase detection signal from of a plurality of clock polyphase signals of an oversampled signal. The detector comprises a plurality of carrier phase detectors, a plurality of variance estimation units, a selection unit and an output unit. Each phase detector determines the carrier phase of a clock polyphase signal and emits a carrier phase signal corresponding to the carrier phase. Each variance estimation unit determines the variance of one of the carrier phase signals. The selection unit compares the variances of the carrier phase signals with one another and emits a selection signal as the clock phase detection signal for selection of that clock polyphase signal whose associated carrier phase has the smallest variance. The output unit emits at least one of the carrier phase signal as the carrier phase detection signal.