Abstract: A clock generator serves to generate a stable frequency system clock for a clock-controlled electronic device. To ensure that the system clock causes only little electromagnetic interference to nearby electronic equipment, the system clock is modulated with respect to a reference clock by means of a phase modulator controlled by a random signal source which is noise colored by means of a weighting device.

Abstract: An iterative interpolator permits linear interpolation between a first known value and second known value, which are defined by n-coordinate values in an n-dimensional coordinate system. An intermediate value to be interpolated is defined by n-1 intermediate values. By an interval nesting process in a first coordinate direction, an approximate value is formed for the first intermediate value. A copying device transfers this interval nesting process to the required coordinate value in the other coordinate direction.

Abstract: An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal.

Abstract: In an equalizer with n number of frequency ranges for digitized signals in which by means of n-1 cascaded filter circuits containing parallel connected digital low-pass filters and digital high pass filters whose respective frequency responses are linked by complementary transfer functions. A desired amplitude response is implemented via an increase or decrease in the amplitudes of adjacent frequency ranges in the associated filter circuit by weighting the outputs of the digital high-pass and low-pass filters, and a control unit forms the respective weighting factor from an equalizer control signal which contains the desired amplitude response as information.

Abstract: A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.