Patents by Inventor Anh Phan

Anh Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240406715
    Abstract: Embodiments herein relate to method performed by a UE (102) having multiple SIMs for simultaneous communication with two or more wireless communications networks. The UE (102) provides, to a first network node (104) associated with a first wireless communications network associated with a first SIM, information on full capability of the UE (102), wherein the UE (102) is registered with the first wireless communications network. The UE further provides, to a second network node (106) associated with a second wireless communications network associated with a second SIM, the information on the full capability of the UE (102), wherein the CE (102) is registered with the second wireless communications network such that the UE (102) is simultaneously registered with the first wireless communications network and the second wireless communications network.
    Type: Application
    Filed: October 5, 2022
    Publication date: December 5, 2024
    Inventors: Mai-Anh Phan, Hernán Felipe Arraño Scharager, Paul Schliwa-Bertling, Lian Araujo, Magnus Stattin
  • Patent number: 12160752
    Abstract: Methods and apparatus are provided. In an example aspect, a method of transmitting data is provided. The method comprises determining if a first channel on a first cell is occupied and, if the first channel on the first cell is occupied for at least a predetermined period, transmitting the data on a second channel on a second cell.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 3, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Torsten Dudda, Reem Karaki, Hubertus Munz, Dhruvin Patel, Mai-Anh Phan, Alexandros Palaios
  • Patent number: 12148806
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Publication number: 20240371700
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Intel Corporation
    Inventors: Aaron D. LILAK, Ehren MANNEBACH, Anh PHAN, Richard E. SCHENKER, Stephanie A. BOJARSKI, Willy RACHMADY, Patrick R. MORROW, Jeffrey D. BIELEFELD, Gilbert DEWEY, Hui Jae YOO
  • Patent number: 12133085
    Abstract: Methods and apparatus are provided. In an example aspect, a method of transmitting data is provided. The method comprises determining if a first channel on a first cell is occupied and, if the first channel on the first cell is occupied for at least a predetermined period, transmitting the data on a second channel on a second cell.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: October 29, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Torsten Dudda, Reem Karaki, Hubertus Munz, Dhruvin Patel, Mai-Anh Phan, Alexandros Palaios
  • Patent number: 12107085
    Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher Jezewski, Ehren Mannebach, Rishabh Mehandru, Patrick Morrow, Anand S. Murthy, Anh Phan, Willy Rachmady
  • Patent number: 12096489
    Abstract: A method performed by a wireless device. The method may be understood to be for handling a random access procedure in a wireless communications network via a network node. The wireless device operates in the wireless communications network. The wireless device refrains, after having sent a first message to the network node requesting random access and having received a first random access response message from the network node, from stopping a timer. The timer is for a time window for receiving the random access response message. The wireless device also continues monitoring both: a) a radio channel for further random access response messages from the network node addressed to a temporary identifier, and b) the radio channel, addressed to a temporary identifier specifically addressing the wireless device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 17, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Min Wang, Marco Belleschi, Jan Christoffersson, Mai-Anh Phan, Johan Rune, Robert Karlsson
  • Patent number: 12080605
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick R. Morrow, Jeffrey D. Bielefeld, Gilbert Dewey, Hui Jae Yoo
  • Publication number: 20240276359
    Abstract: A method performed by a radio network node for handling services in a wireless communications network. The radio network node receives, from a user equipment (UE), an indication indicating selection of a service associated with a service indication out of at least one service indication; and based on the received indication, selects a network node that supports the service indicated by the indication.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 15, 2024
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Christofer LINDHEIMER, Mai-Anh PHAN, Oscar OHLSSON, Hernán Felipe ARRAÑO SCHARAGER, Miguel Angel GARCIA MARTIN, Peter HEDMAN
  • Publication number: 20240276508
    Abstract: New signaling is defined from wireless devices to a wireless communication network, concerning the wireless devices' duty cycle statuses. This allows the network to optimize its control of the radio resource usage. Additionally, embodiments described herein provide new signalling from the network to wireless devices concerning the network's duty cycle status. This allows wireless devices to optimize their idle mode operation, including decisions whether to request a connection setup or remain in idle mode. Embodiments described and claimed herein provide a set of simple methods for operating a cellular system in a duty cycle controlled radio frequency band.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Inventors: Olof Liberg, David Sugirtharaj, Emma Wittenmark, Mai-Anh Phan
  • Publication number: 20240234422
    Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 11, 2024
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Anh PHAN, Nicole K. THOMAS, Urusa ALAAN, Seung Hoon SUNG, Christopher M. NEUMANN, Willy RACHMADY, Patrick MORROW, Hui Jae YOO, Richard E. SCHENKER, Marko RADOSAVLJEVIC, Jack T. KAVALIEROS, Ehren MANNEBACH
  • Patent number: 12033896
    Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan
  • Patent number: 12020929
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Ehren Mannebach, Patrick Morrow, Anh Phan, Willy Rachmady, Hui Jae Yoo
  • Patent number: 12022350
    Abstract: A network-based method allows a network to optimize its control of radio resource usage by directing connected and idle mode User Equipment (UEs) (10) to another network node, e.g. a neighbor cell, having a better duty cycle, or by configuring the UEs to use another frequency band served by the same network node or a different network node. Signaling its duty cycle budget to the UEs allows the UEs to optimize their idle mode operation by performing cell reselection to a network node which has a better duty cycle budget.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: June 25, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Olof Liberg, David Sugirtharaj, Emma Wittenmark, Mai-Anh Phan
  • Publication number: 20240186398
    Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Aaron D. LILAK, Anh PHAN, Rishabh MEHANDRU, Stephen M. CEA, Patrick MORROW, Jack T. KAVALIEROS, Justin WEBER, Salim BERRADA
  • Patent number: 11996411
    Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung, Christopher M. Neumann, Willy Rachmady, Patrick Morrow, Hui Jae Yoo, Richard E. Schenker, Marko Radosavljevic, Jack T. Kavalieros, Ehren Mannebach
  • Patent number: 11996408
    Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey, Orb Acton, Willy Rachmady
  • Publication number: 20240172095
    Abstract: A method performed by a radio network node (12) for handling communication in a wireless communications network. The radio network node (12) configures a UE (10) with a mapping, wherein the mapping maps a name indication to a GID, and/or a type indication of a type of service offered by one or more networks identified by the GID.
    Type: Application
    Filed: March 29, 2022
    Publication date: May 23, 2024
    Inventors: Christofer Lindheimer, Mai-Anh Phan, Oscar Ohlsson, Hernán Felipe Arraño Scharager, Miguel Angel Garcia Martin, Peter Hedman
  • Patent number: 11991710
    Abstract: New signaling is defined from wireless devices (10) to a wireless communication network, concerning the wireless devices' duty cycle statuses. This allows the network to optimize its control of the radio resource usage. Additionally, embodiments described herein provide new signalling from the network to wireless devices concerning the network's duty cycle status. This allows wireless devices (10) to optimize their idle mode operation, including decisions whether to request a connection setup or remain in idle mode. Embodiments described and claimed herein provide a set of simple methods for operating a cellular system in a duty cycle controlled radio frequency band.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 21, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Olof Liberg, David Sugirtharaj, Emma Wittenmark, Mai-Anh Phan
  • Publication number: 20240162141
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 16, 2024
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU