Abstract: Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

Abstract: A method performed by a wireless device. The method may be understood to be for handling a random access procedure in a wireless communications network via a network node. The wireless device operates in the wireless communications network. The wireless device refrains, after having sent a first message to the network node requesting random access and having received a first random access response message from the network node, from stopping a timer. The timer is for a time window for receiving the random access response message. The wireless device also continues monitoring both: a) a radio channel for further random access response messages from the network node addressed to a temporary identifier, and b) the radio channel, addressed to a temporary identifier specifically addressing the wireless device.

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

Abstract: One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.

Abstract: A method and a terminal for acquiring paging information during a set of one or more paging occasions, one paging occasion corresponding to a subframe. In an embodiment, the method determines a first subframe of the set of one or more paging occasions and determines a last subframe of the set of one or more paging occasions. The terminal is required to attempt to acquire the paging information in any subframe between the first subframe and the last subframe of the set of one or more paging occasions.

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

Abstract: A method performed by a wireless communication device for reducing handover delay, wherein the wireless communication device is arranged to operate in a cellular communication system and to operate in a cell using unlicensed spectrum. The method includes receiving a downlink, DL, signal from network node operating a neighbouring cell operating in the unlicensed spectrum, wherein the DL signal includes a discovery reference signal, DRS, subframe, storing data associated with the DRS subframe, receiving a handover command from a network node operating a serving cell where the neighbouring cell is a target cell, and performing a random access procedure for handover to the target cell. A device performing the method and a computer program for implementing the method are also disclosed.

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

Abstract: A method performed by a wireless communication device for reducing handover delay, wherein the wireless communication device is arranged to operate in a cellular communication system and to operate in a cell using unlicensed spectrum. The method includes receiving a downlink, DL, signal from network node operating a neighbouring cell operating in the unlicensed spectrum, wherein the DL signal includes a discovery reference signal, DRS, subframe, storing data associated with the DRS subframe, receiving a handover command from a network node operating a serving cell where the neighbouring cell is a target cell, and performing a random access procedure for handover to the target cell. A device performing the method and a computer program for implementing the method are also disclosed.

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

Abstract: There is provided a method, in a wireless device, for communicating with a network node using autonomous Uplink (UL) access. The method comprises: after sending a data transmission to a network node, starting a retransmission window associated with a feedback process of the data transmission, the retransmission window including a first timer; and in response to detecting an absence of a feedback signal during a time period given by the first timer, retransmitting the data after expiry of the first timer.

Abstract: New signaling is defined from wireless devices (10) to a wireless communication network, concerning the wireless devices' duty cycle statuses. This allows the network to optimize its control of the radio resource usage. Additionally, embodiments described herein provide new signalling from the network to wireless devices concerning the network's duty cycle status. This allows wireless devices (10) to optimize their idle mode operation, including decisions whether to request a connection setup or remain in idle mode. Embodiments described and claimed herein provide a set of simple methods for operating a cellular system in a duty cycle controlled radio frequency band.

Abstract: In an embodiment, a method and a terminal for acquiring paging information during a set of one or more paging occasions, one paging occasion corresponding to a subframe. In an embodiment, the method determines a first subframe of the set of one or more paging occasions and determines a last subframe of the set of one or more paging occasions.

Abstract: Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension. A dielectric material between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure.

Abstract: A network-based method allows a network to optimize its control of radio resource usage by directing connected and idle mode User Equipment (UEs) (10) to another network node, e.g. a neighbor cell, having a better duty cycle, or by configuring the UEs to use another frequency band served by the same network node or a different network node. Signaling its duty cycle budget to the UEs allows the UEs to optimize their idle mode operation by performing cell re-selection to a network node which has a better duty cycle budget.

Abstract: According to an aspect, a wireless device identifies system frame numbers (SFNs) that are used for wireless transmissions that use a broadcast channel (BCH) transmission time interval (TTI), where frequency hopping cycles (FHCs) are not aligned with a cycle of the SFNs. The wireless device receives FH information indicating how the FHC used for wireless transmissions relates to the SFN cycle and identifies an SFN timing for the wireless transmissions based on the FH information.

Abstract: A calibration system for a food processing machine has a conveyor for conveying a workpiece, scanning system for scanning the workpiece and creating a digital image of the workpiece, and a cutting device downstream from the scanning system for cutting the workpiece. A calibration object is conveyed through the food processing machine by the conveyor and scanned. A controller, with a memory, is in communication with the cutting device and the conveyor such that the controller can track position of the cutting device as the cutting device is moved into alignment with the calibration object and store calibration values on the memory corresponding to the movement of the cutting device into alignment with the calibration object. The controller is configured to calibrate movement of the cutting device relative to the workpiece based on the digital image of the workpiece and the calibration values to thereafter accurately cut the workpiece.

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).