Patents by Inventor Anh Phan

Anh Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186398
    Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Aaron D. LILAK, Anh PHAN, Rishabh MEHANDRU, Stephen M. CEA, Patrick MORROW, Jack T. KAVALIEROS, Justin WEBER, Salim BERRADA
  • Patent number: 11996411
    Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung, Christopher M. Neumann, Willy Rachmady, Patrick Morrow, Hui Jae Yoo, Richard E. Schenker, Marko Radosavljevic, Jack T. Kavalieros, Ehren Mannebach
  • Patent number: 11996408
    Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey, Orb Acton, Willy Rachmady
  • Publication number: 20240172095
    Abstract: A method performed by a radio network node (12) for handling communication in a wireless communications network. The radio network node (12) configures a UE (10) with a mapping, wherein the mapping maps a name indication to a GID, and/or a type indication of a type of service offered by one or more networks identified by the GID.
    Type: Application
    Filed: March 29, 2022
    Publication date: May 23, 2024
    Inventors: Christofer Lindheimer, Mai-Anh Phan, Oscar Ohlsson, Hernán Felipe Arraño Scharager, Miguel Angel Garcia Martin, Peter Hedman
  • Patent number: 11991710
    Abstract: New signaling is defined from wireless devices (10) to a wireless communication network, concerning the wireless devices' duty cycle statuses. This allows the network to optimize its control of the radio resource usage. Additionally, embodiments described herein provide new signalling from the network to wireless devices concerning the network's duty cycle status. This allows wireless devices (10) to optimize their idle mode operation, including decisions whether to request a connection setup or remain in idle mode. Embodiments described and claimed herein provide a set of simple methods for operating a cellular system in a duty cycle controlled radio frequency band.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 21, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Olof Liberg, David Sugirtharaj, Emma Wittenmark, Mai-Anh Phan
  • Publication number: 20240162141
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 16, 2024
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU
  • Publication number: 20240145557
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY
  • Patent number: 11950157
    Abstract: Methods, nodes and computer program products control radio channel deployment when using un-licensed carriers in a wireless communication network and control mobility and/or load balancing target selection when using un-licensed carriers. When performed in an access node, unlicensed carrier intrinsic cell channel load is determined in a cell served by the access node based on one or more predetermined channel load indicators and neighbor cell channel load information is obtained, from one or more neighboring access nodes. The neighbor cell channel load information includes unlicensed carrier channel load in respective cells based on the one or more predetermined channel load indicators. At least one channel deployment operation is initiated based on an outcome of one or more comparative operations including the determined unlicensed carrier intrinsic cell channel load and/or the obtained neighbor cell channel load information.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 2, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chunhui Zhang, Peter Alriksson, Tomas Hedberg, Yusheng Liu, Mai-Anh Phan, David Sugirtharaj, Emma Wittenmark
  • Patent number: 11942416
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Rishabh Mehandru
  • Patent number: 11916118
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Publication number: 20240047559
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventors: Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Patrick MORROW, Anh PHAN, Cheng-Ying HUANG, Ehren MANNEBACH
  • Patent number: 11894372
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
  • Patent number: 11864722
    Abstract: Methods and systems for adjusting ventilator settings in a patient based on information obtained by measuring anatomical dead space VD in a lung are provided utilizing controlled indicator gas delivery over multiple breaths, including related measurements and calculations of lung inhomogeneity, functional residual capacity, avelolar volume VA, dead space VD, and pulmonary blood flow {dot over (Q)}P.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 9, 2024
    Assignee: VENTDX, INC.
    Inventors: Phi Anh Phan, Andrew Farmery, Clive Hahn
  • Patent number: 11869894
    Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
  • Patent number: 11830933
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Patrick Morrow, Anh Phan, Cheng-Ying Huang, Ehren Mannebach
  • Publication number: 20230377947
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 23, 2023
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
  • Publication number: 20230369399
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Ehren MANNEBACH, Anh PHAN, Aaron LILAK, Willy RACHMADY, Gilbert DEWEY, Cheng-Ying HUANG, Richard SCHENKER, Hui Jae YOO, Patrick MORROW
  • Publication number: 20230352481
    Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Inventors: Aaron D. LILAK, Gilbert DEWEY, Cheng-Ying HUANG, Christopher JEZEWSKI, Ehren MANNEBACH, Rishabh MEHANDRU, Patrick MORROW, Anand S. MURTHY, Anh PHAN, Willy RACHMADY
  • Publication number: 20230337096
    Abstract: A network-based method allows a network to optimize its control of radio resource usage by directing connected and idle mode User Equipment (UEs) (10) to another network node, e.g. a neighbor cell, having a better duty cycle, or by configuring the UEs to use another frequency band served by the same network node or a different network node. Signaling its duty cycle budget to the UEs allows the UEs to optimize their idle mode operation by performing cell re-selection to a network node which has a better duty cycle budget.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Olof Liberg, David Sugirtharaj, Emma Wittenmark, Mai-Anh Phan
  • Patent number: 11776898
    Abstract: Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Anh Phan, Gilbert Dewey, Willy Rachmady, Patrick Morrow