Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump on leadframe (BOL) processes in accordance with embodiments of the present invention increase the space available to the die for a given package footprint. Embodiments of the present invention may also permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

Abstract: A leadframe having raised features for use a semiconductor device package, is fabricated by bonding together at least two metal layers. A first metal layer may define the lateral dimensions of the leadframe, including any diepad and leads. A second metal layer bonded to the first metal layer, may define the raised features of the leadframe, such as steps for physically securing the leadframe within the package body. The multiple metal layers may be bonded together by a number of possible techniques, including but not limited to ultrasonic welding, soft soldering, or the use of epoxy. Prior to or after bonding, one or more of the metal layers may be coined or stamped to form additional features such as offsets or channels.

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Abstract: Singulation of individual electronic packages fabricated as part of a common matrix, is accomplished by mask patterning and chemical exposure in combination with physical sawing. In one embodiment of a singulation process in accordance with the present invention, an initial, shallow saw cut into inter-package regions of the matrix exposes underlying metal to subsequent chemical etching steps. In an alternative embodiment, a separate photoresist mask may be patterned over the matrix to selectively expose metal in inter-package regions to chemical etching.

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.