Patents by Inventor Anton Mauder

Anton Mauder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226015
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Andreas Peter Meiser, Caspar Leendertz, Anton Mauder
  • Publication number: 20210226072
    Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body; and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 22, 2021
    Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
  • Patent number: 11069626
    Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Hanno Melzner, Stefan Miethaner, Sebastian Schmidt, Hans-Joachim Schulze
  • Publication number: 20210193646
    Abstract: A single chip power semiconductor device includes: first and second load terminals; a semiconductor body integrated in the single chip and coupled to the load terminals and configured to conduct a load current along a load current path between the load terminals; a control terminal and at least one control electrode electrically connected thereto, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; a protection structure integrated, separately from the load current path, in the single chip and including a series connection of pn junctions with first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The series connection of the pn-junctions is connected in forward bias between the control terminal and the first load terminal.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Inventors: Guang Zeng, Anton Mauder, Joachim Weyers
  • Publication number: 20210183746
    Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11018051
    Abstract: A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11018249
    Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Matteo Dainese, Elmar Falck, Franz-Josef Niedernostheide, Manfred Pfaffenlehner
  • Patent number: 11011606
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Publication number: 20210134960
    Abstract: A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 6, 2021
    Inventors: Ralf Siemieniec, Rudolf Elpelt, Anton Mauder
  • Patent number: 10989742
    Abstract: A current sensor and a current sensing method are disclosed. The current sensor includes a sensor chip having a first chip surface, a second chip surface and at least one sensor element, and a housing having a first housing surface adjoining the second chip surface and a second housing surface spaced apart from the first housing surface and separated from the first housing surface by a spacer section of the housing. The second housing surface is configured to be mounted on a conductor and is electrically insulating.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 27, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Martin Gruber, Goran Keser
  • Patent number: 10991832
    Abstract: A power diode includes a semiconductor body coupled to an anode metallization and to a cathode metallization. The semiconductor body has a drift region of a first conductivity type and an anode region of a second conductivity type. The anode region includes: a contact zone arranged in contact with the anode metallization; a field stop zone arranged below the contact zone; and a body zone arranged below the field stop zone and above the drift region. An electrically activated dopant concentration of the anode region has a profile, along a vertical direction, according to which: a first maximum is present within the contact zone; a second maximum is present within the field stop zone; and the dopant concentration continuously decreases from the first maximum to a local minimum, and continuously increases from the local minimum to the second maximum.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 27, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Barusic
  • Patent number: 10985248
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Caspar Leendertz, Romain Esteve, Anton Mauder, Andreas Meiser, Bernd Zippelius
  • Patent number: 10978596
    Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
  • Patent number: 10971435
    Abstract: A semiconductor device includes a bonding pad that includes a base portion having a base layer. A bond wire or clip is bonded to a bonding region of a main surface of the bonding pad. A supplemental structure is in direct contact with the base portion next to the bonding region. A specific heat capacity of the supplemental structure is higher than a specific heat capacity of the base layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Patent number: 10971620
    Abstract: A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Joachim Weyers, Andreas Boehm, Anton Mauder, Patrick Schindler, Stefan Tegen, Armin Tilke, Uwe Wahl
  • Patent number: 10950718
    Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Anton Mauder, Thomas Kuenzig, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Publication number: 20210028119
    Abstract: A power semiconductor device is proposed. The power semiconductor device includes a semiconductor substrate. The power semiconductor device further includes an electrically conducting first layer. At least part of the electrically conducting first layer includes pores. The power semiconductor device further includes an electrically conducting second layer. The electrically conducting second layer is arranged between the semiconductor substrate and the electrically conducting first layer. The pores are at least partially filled with a phase change material.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 28, 2021
    Inventors: Fabian Streb, Anton Mauder, Stephan Pindl, Hans-Joachim Schulze
  • Patent number: 10903322
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 10903353
    Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 26, 2021
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen
  • Patent number: 10903347
    Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Anton Mauder, Thomas Kuenzig, Franz-Josef Niedernostheide, Christian Philipp Sandow