Patents by Inventor Anton Mauder

Anton Mauder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113512
    Abstract: A method of producing a power semiconductor device includes: providing a semiconductor body with a vertically protruding fin covered by an insulation material covered by an electrode material, and an insulating material at least partially covering the electrode material; exposing a portion of the electrode material arranged above an upper portion of the fin; removing the exposed portion of the electrode material to expose the upper portion of the fin, thereby forming a respective recess adjacent to both sides of the exposed upper portion of the fin, the recesses being spatially confined by the insulation material, the electrode material and the insulating material; forming an ILD on top of the exposed portions of the device; and forming a first load terminal above the ILD and configured to contact the upper portion of the fin.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Inventors: Anton Mauder, Hans-Jürgen Thees
  • Publication number: 20250113583
    Abstract: A power semiconductor device includes: a semiconductor body with a vertically protruding fin configured to conduct a portion of a nominal load current of the device; and a first load terminal in contact with an upper portion of the fin. An electrode material is arranged adjacent to the fin and electrically insulated from the fin by insulation material. The electrode material is electrically insulated from the first load terminal by an insulating material. The power semiconductor device further includes, on top of the electrode material, insulating sidewall spacers adjacent to the insulating material and the insulation material. The sidewall spacers terminate at a pull-back distance below the top of the fin. The pull-back distance amounts to at least 90% of a width of the fin at the top of the fin.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Inventors: Hans-Jürgen Thees, Anton Mauder
  • Patent number: 12266718
    Abstract: A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies AG
    Inventors: Hans-Juergen Thees, Alim Karmous, Anton Mauder
  • Patent number: 12266680
    Abstract: A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area AQ, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m?*cm2/AQ.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Christian Philipp Sandow, Anton Mauder, Franz-Josef Niedernostheide
  • Patent number: 12218029
    Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Anton Mauder, Stephan Voss, Martin Gruber
  • Patent number: 12211945
    Abstract: A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Mario Barusic, Markus Beninger-Bina, Matteo Dainese
  • Publication number: 20240363700
    Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Lars Mueller-Meskamp, Ralf Rudolf, Anton Mauder, Annett Winzer, Dirk Priefert, Christian Schippel, Thomas Kuenzig
  • Patent number: 12132122
    Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: October 29, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Guang Zeng, Moritz Hauf, Anton Mauder
  • Publication number: 20240275379
    Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 15, 2024
    Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder
  • Patent number: 12003231
    Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 4, 2024
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder
  • Publication number: 20240113053
    Abstract: The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.
    Type: Application
    Filed: September 14, 2023
    Publication date: April 4, 2024
    Inventors: Andreas Korzenietz, Anton Mauder, Christoffer Erbert, Julia Zischang
  • Publication number: 20240113705
    Abstract: A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventors: Anton Mauder, Massimo Grasso, Edward Fürgut
  • Patent number: 11949006
    Abstract: A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: April 2, 2024
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20240063216
    Abstract: A semiconductor device includes: a transistor formed in a first semiconductor layer stack; a diode formed in a second semiconductor layer stack, the diode including an anode metal layer; and a carrier. The transistor and the diode are mounted to the carrier. A terminal of the transistor is electrically connected to the carrier, and the anode metal layer is in direct contact with the carrier.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 22, 2024
    Inventors: Digvijay Raghunathan, Anton Mauder
  • Patent number: 11848377
    Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: December 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Matteo Dainese, Elmar Falck, Franz-Josef Niedernostheide, Manfred Pfaffenlehner
  • Patent number: 11837528
    Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20230307554
    Abstract: A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Anton Mauder, Mario Barusic, Markus Beninger-Bina, Matteo Dainese
  • Patent number: 11764296
    Abstract: A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: September 19, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20230290885
    Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.
    Type: Application
    Filed: April 19, 2023
    Publication date: September 14, 2023
    Inventors: Guang Zeng, Moritz Hauf, Anton Mauder
  • Publication number: 20230282736
    Abstract: A semiconductor die includes: a semiconductor substrate; transistor cells formed in a first region of the semiconductor substrate and electrically coupled in parallel to form a power transistor, the transistor cells including first trenches that extend from a first surface of the semiconductor substrate into the first region; a gate pad formed above the first surface and electrically connected to gate electrodes in the first trenches, the gate pad being formed over a second region of the semiconductor substrate that is devoid of functional transistor cells; second trenches extending from the first surface into the second region and including gate electrodes that are electrically connected to the gate pad and form a first conductor of an additional input capacitance of the power transistor; and a second conductor of the additional input capacitance formed in the second region adjacent the second trenches. Methods of producing the semiconductor die are also described.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Inventors: Rabie Djemour, Hannes Mathias Geike, Anton Mauder