Patents by Inventor Anton Mauder

Anton Mauder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200259007
    Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.
    Type: Application
    Filed: May 1, 2020
    Publication date: August 13, 2020
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 10734484
    Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Anton Mauder, Roland Rupp, Oana Julia Spulber
  • Publication number: 20200243340
    Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10707865
    Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Martina Seider-Schmidt, Hans-Joachim Schulze, Oliver Hellmund, Sebastian Schmidt, Peter Irsigler
  • Patent number: 10693456
    Abstract: A method and an electronic circuit are disclosed. The method includes driving a transistor device in an on-state by applying a drive voltage higher than a threshold voltage of the transistor device to a drive input, and adjusting a voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device, wherein the current level is an actual current level or an expected current level of the load current.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies AG
    Inventors: Werner Roessler, Anton Mauder
  • Patent number: 10679857
    Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10679855
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Publication number: 20200176568
    Abstract: A semiconductor device includes a silicon carbide semiconductor body including a source region of a first conductivity type, a body region of a second conductivity type, shielding regions of the second conductivity type and compensation regions of the second conductivity type. Trench structures extend from a first surface into the silicon carbide semiconductor body along a vertical direction. Each of the trench structures includes an auxiliary electrode at a bottom of the trench structure and a gate electrode between the auxiliary electrode and the first surface. The auxiliary electrode is electrically insulated from the gate electrode. The auxiliary electrode of each of the trench structures is adjoined by at least one of the shielding regions at the bottom of the trench structure. Each of the shielding regions is adjoined by at least one of the compensation regions at the bottom of the shielding region.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 4, 2020
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Patent number: 10672767
    Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 10665706
    Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Publication number: 20200161437
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Publication number: 20200161433
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Application
    Filed: March 15, 2019
    Publication date: May 21, 2020
    Inventors: Caspar Leendertz, Romain Esteve, Anton Mauder, Andreas Meiser, Bernd Zippelius
  • Patent number: 10658457
    Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 19, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Anton Mauder
  • Publication number: 20200152743
    Abstract: A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Patent number: 10651037
    Abstract: One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes irradiating the semiconductor body via the one side with further particles at least in the region containing the dopant particles. The method finally includes carrying out a thermal treatment by means of which the semiconductor body is heated, at least in the region containing the dopant particles, to a predetermined temperature in order to activate the implanted dopant particles, said temperature being less than 700° C.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Helmut Strack, Holger Schulze
  • Publication number: 20200136608
    Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 30, 2020
    Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder
  • Publication number: 20200111874
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 10615254
    Abstract: An embodiment of a semiconductor device includes a SiC semiconductor body region having a body region of a first conductivity type, a drift zone of a second conductivity type, and a compensation structure of the first conductivity type. The compensation structure and a drift zone section of the drift zone form a super junction structure. The compensation structure adjoins the body region and is positioned entirely below the body region in a vertical direction perpendicular to a surface of the SiC semiconductor body. The compensation structure includes a first compensation sub-structure and a second compensation sub-structure. The first compensation sub-structure and the second compensation sub-structure are arranged above one another in the vertical direction. A width of the compensation structure changes along the vertical direction.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Rudolf Elpelt, Dethard Peters
  • Patent number: 10586851
    Abstract: A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface. A shielding region adjoins the auxiliary electrode at the bottom of the trench structure and forms a first pn junction with a drift structure. A corresponding method of manufacturing the semiconductor device is also described.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Publication number: 20200066579
    Abstract: A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 27, 2020
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze