Abstract: A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time that the change in current through the power switch is in regulation, and comparing the time that the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time that the change in current through the power switch is in excess of the reference time.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.

Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.

Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.

Abstract: A semiconductor device includes a bonding pad that includes a base portion having a base layer. A bond wire or clip is bonded to a bonding region of a main surface of the bonding pad. A supplemental structure is in direct contact with the base portion next to the bonding region. A specific heat capacity of the supplemental structure is higher than a specific heat capacity of the base layer.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

Abstract: According to an embodiment of a switch device, the switch device includes a first switch, a second switch and an evaluation circuit. The evaluation circuit is configured to evaluate a temporal behavior of a node between the first switch and the second switch to detect a possible fault condition of at least one of the first switch or the second switch. A corresponding fault detection method for a switch device having a first switch and a second switch is also provided.

Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.

Abstract: A power semiconductor transistor includes a trench extending into a semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom, an electrode in the trench electrically insulated from the semiconductor body, drift and source regions of a first conductivity type, a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source and drift regions, and a guidance zone. The guidance zone includes a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, and a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region. The plateau section has at least one opening below the channel region.

Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

Abstract: A method and an electronic circuit are disclosed. The method includes driving a transistor device in an on-state by applying a drive voltage higher than a threshold voltage of the transistor device to a drive input, and adjusting a voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device, wherein the current level is an actual current level or an expected current level of the load current.