Patents by Inventor Ariel Navon

Ariel Navon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220138541
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.
    Type: Application
    Filed: February 24, 2021
    Publication date: May 5, 2022
    Inventors: Alexander Bazarsky, Ariel Navon, Ofir Pele
  • Publication number: 20220107893
    Abstract: The present disclosure generally relates to improving write cache utilization by recommending a time to initiate a data flush operation or predicting when a new write command will arrive. The recommending can be based upon considerations such as a hard time limit for data caching, rewarding for filling the cache, and penalizing for holding data for too long. The predicting can be based on tracking write command arrivals and then, based upon the tracking, predicting an estimated arrival time for the next write command. Based upon the recommendation or predicting, the write cache can be flushed or the data can remain in the write cache to thus more efficiently utilize the write cache without violating a hard stop time limit.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Ariel NAVON
  • Patent number: 11294595
    Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky
  • Patent number: 11281981
    Abstract: A storage system and sorting-based method for random read command prediction in a multi-queue system are provided. In one embodiment, a method for command prediction is performed in a storage system comprising a memory and being in communication with a host. The method comprises receiving a read command sequence from the host, wherein read commands in the read command sequence originate from a plurality of command queues in the host such that read commands in the read command sequence received from the host are out of order; sorting read commands in the read command sequence received from the host based on logical block addresses; and predicting a next read command from the sorted read commands. Other embodiments are provided.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Shay Benisty
  • Patent number: 11269645
    Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Ran Zamir, Shay Benisty
  • Patent number: 11269764
    Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Alexander Bazarsky, Ariel Navon, David Gur
  • Publication number: 20220036945
    Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir
  • Publication number: 20220019443
    Abstract: The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Inventors: Shay BENISTY, Judah Gamliel HAHN, Ariel NAVON
  • Patent number: 11216696
    Abstract: Exemplary methods and apparatus are provided for configuring a data storage controller to select training data samples from a non-volatile memory (NVM) array for forwarding to an external machine learning processor. The machine learning processor trains a deep neural network model by, e.g., performing various forward and backward passes through a neural network. Within illustrative examples, the data storage controller is equipped with a data sample selection unit that intelligently selects training data stored in the NVM array to forward to the external machine learning processor to reduce an amount of training data to be transferred to the machine learning processor. Among other features, this allows for the practical use of NVM arrays (such as NAND memory arrays) for storing large quantities of machine learning training data, rather than high-speed volatile memory (such as dynamic random access memory), which may be impractical and cost-prohibitive for low-power applications.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 4, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Shay Benisty
  • Publication number: 20210405731
    Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Eran Sharon, Shay Benisty
  • Publication number: 20210405911
    Abstract: Systems and methods for compacting and anonymizing telemetry data in a storage system. A controller of a storage device may generate telemetry data based on collected features indicative of the performance of the storage device. The controller may store the telemetry data in the telemetry memory of the storage device. The controller may then transform the telemetry data into transformed telemetry data based on a dimension reduction algorithm, and transmit the transformed telemetry data to the host device.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn
  • Patent number: 11210183
    Abstract: Example systems and methods provide differentiated data recovery configurations based on memory health data. A distributed storage system, such as a cloud-based storage system, stores backup data from a remote storage device using a first data recovery configuration. Based on memory health data collected from the remote storage device, a change in a memory health state of the remote storage device may be determined. Responsive to the change in the memory health state, a different data recovery configuration may be used for storing backup data going forward and reallocating previously stored backup data in the distributed storage system.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Alex Bazarsky, Eran Sharon, Idan Alrod
  • Publication number: 20210389888
    Abstract: The present disclosure generally relates to systems and methods by which a data storage device may receive data about the host system in which it is installed, and the customer associated with that system. Based upon this received data, the data storage device may modify its native operating parameters and custom functions to enable more optimal operation with the host system.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Judah Gamliel HAHN, Shay BENISTY, Ariel NAVON
  • Publication number: 20210390179
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Shay Benisty, Ariel Navon
  • Patent number: 11194489
    Abstract: The present disclosure generally relates to a flexible or soft architecture solution of a host-data storage device system. The host is permitted different, intermediate levels of responsibility to the memory management. The different levels of host involvement in the memory management of the memory device are anywhere between an existing zone namespace (ZNS) solution and an open channel solution. The data storage device offers a selection of specific memory management options to the host device. The host device then selects the level of memory management desired and configures the data storage device to meet the memory management selection. In so doing, the host device controls the trade-off between host device overhead of memory management and host device flexibility.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 7, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Idan Alrod, Shay Benisty, Ariel Navon, Judah Gamliel Hahn
  • Patent number: 11188256
    Abstract: Enhanced read-ahead capabilities for storage devices are disclosed herein. In an implementation, data for a given write operation may be written to storage such that the location of the next write is stored with the data. Later, when the data is being read from storage, other data may be pre-fetched from the location of the next write that was written with the data. If the next location is the target of a subsequent read operation, the other data may be returned to the host immediately, since it will have already been read from the location where it was stored, thereby speeding-up the subsequent read operation.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Eliash, Ariel Navon, Roy Peretz
  • Patent number: 11188456
    Abstract: A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 30, 2021
    Inventors: Ariel Navon, Micha Yonin, Alexander Bazarsky, Judah Gamliel Hahn, David Gur, Omer Fainzilber
  • Patent number: 11182101
    Abstract: A storage system and method for stream management in a multi-host virtualized storage system are provided. In one embodiment, a method for stream management is provided that is performed in a storage system in communication with a host comprising a plurality of virtual hosts. The method comprises: receiving, from the host, identification of each virtual host of the plurality of virtual hosts; analyzing usage history of each virtual host of the plurality of virtual hosts; and assigning streams to a subset of the plurality of virtual hosts based on the usage history, wherein a maximum number of streams assignable by the storage system is less than a total number of virtual hosts in the plurality of virtual hosts. Other embodiments are provided.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Ariel Navon, Shay Benisty, Judah Gamliel Hahn
  • Publication number: 20210334022
    Abstract: The present disclosure generally relates to a flexible or soft architecture solution of a host-data storage device system. The host is permitted different, intermediate levels of responsibility to the memory management. The different levels of host involvement in the memory management of the memory device are anywhere between an existing zone namespace (ZNS) solution and an open channel solution. The data storage device offers a selection of specific memory management options to the host device. The host device then selects the level of memory management desired and configures the data storage device to meet the memory management selection. In so doing, the host device controls the trade-off between host device overhead of memory management and host device flexibility.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Idan ALROD, Shay BENISTY, Ariel NAVON, Judah Gamliel HAHN
  • Patent number: 11158369
    Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 26, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir