Abstract: In one embodiment, the disclosure teaches an apparatus including a memory array and a processor in communication with the memory array. The processor is configured to determine health scores of blocks of the memory array, where the health scores indicate the health of the blocks. The processor also is configured to receive data from a host, and select an interleaving scheme for programming the data based on the data type and a block to which the data is written based on the health scores. In one embodiment, sequential type data is written to unhealthy blocks and non-sequential data is written to healthy blocks.

Abstract: Systems and methods for managing performance and quality of service (QoS) with multiple namespace resource allocation. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe may support the use of namespaces. Namespace configuration may be modified to include performance criteria specific to each namespace. The memory device may then receive commands directed to specific namespaces an apply memory device resources to commands in each namespace queue such that QoS may be applied to control execution of commands such that commands in each namespace receive resources based on host selected performance parameters for each namespace.

Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a storage device is receiving random read commands to non-sequentially addressed data locations from a plurality of host sources are disclosed. A storage device having a memory with a plurality of separate prior read command data structures includes a controller having a next read command prediction module that separately predicts a next read command based on a received read command from the one of the plurality of prior read command data structures associated with the host from which the received command originated. The storage device then pre-fetches the data identified in the predicted next read command.

Abstract: A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.

Abstract: A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.

Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Abstract: Various method and apparatus embodiments for data dependent error correction code (ECC) encoding are disclosed. In one embodiment, a data object may include multiple portions, with each portion having different characteristics. An ECC encoder may allocate error correction resources (e.g., parity bits) to the different portions at respectively different data rates (e.g., more error correction resources to some portions relative to other portions). Upon completion of the allocation, the data object and the associated error correction resources are forwarded to a storage medium for storage therein.

Abstract: Storage devices that can perform adaptive management of intermediate storage memory, and methods for use therewith, are described herein. Such a storage device includes non-volatile memory, wherein a portion thereof is designated as intermediate storage (IS) memory and another portion thereof designated as main storage (MS) memory. The IS memory has lower write and read latencies, greater endurance, and lower storage density and capacity than the MS memory. In certain embodiments, a host activity pattern is predicted, a relocation schemes is selected based on the predicted host activity pattern, and the selected relocation scheme is executed to thereby selectively relocate one or more portions of the data from the IS memory to the MS memory in accordance with the selected relocation scheme. The relocation scheme that is selected and executed can change over time. Additionally relocation schemes can be generated based on activity log(s) and thereafter selected for execution.

Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length sequence of prior read commands are generated and compared to a read command history datastore. When a prior pattern of read commands is found corresponding to the search sequence, a next read command that previously followed that search sequence may be used as a predicted next read command and data pre-fetched based on the read command data location information associated with that prior read command that is being used as the predicted read command.

Abstract: A method of transitioning between a sleep mode for a storage device to reduce power consumption and to increase responsiveness includes collecting one or more recent parameters related to host-storage device workload. The host-storage device workload is correlated to project a next host idle time. A transition between a storage sleep mode is determined.

Abstract: Systems and methods for predicting the next host source of a command directed to a storage device, and configuring the storage device with the host memory configuration parameters of that predicted host, are disclosed. A predictive model may be used to identify which of a plurality of different actual or virtual hosts will be sending a next command based on a pattern of prior host origins of commands. The storage device may include a plurality of different memory configuration parameters associated with each different host source and may update the current memory configuration based on the predicted next host origin prior to actual receipt of a next command.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a storage device is receiving random read commands to non-sequentially addressed data locations from a plurality of host sources are disclosed. A storage device having a memory with a plurality of separate prior read command data structures includes a controller having a next read command prediction module that separately predicts a next read command based on a received read command from the one of the plurality of prior read command data structures associated with the host from which the received command originated. The storage device then pre-fetches the data identified in the predicted next read command.

Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method includes generating a prior read command data structure and receiving a current read command. The method may include retrieving from the prior read command data structure a predicted next read command based on the received current read command, and pre-fetching data associated with the predicted next read command. The method may further include that after pre-fetching the data associate with the predicted next read command and prior to receiving a next read command, retrieving from the prior read command data structure a second predicted next read command based on the predicted next read command, and pre-fetching data associated with the second predicted next read command.

Abstract: Systems and methods for permitting flexible use of volatile memory for storing read command prediction data in a memory device, or in a host memory buffer accessible by the memory device, while preserving accuracy in predicting read commands and pre-fetching data are disclosed. The read command prediction data may be in the form of history pattern match table having entries indexed to a search sequence of one or more commands historically preceding the read command in the indexed table entry. A host trigger requesting the limited volatile memory space, a lower power state that is detected, or a memory device-initiated need may trigger generation of and subsequent use of a smaller table for the prediction process while the larger table is released. The memory device may later regenerate the larger table when more space in the volatile memory becomes available.

Abstract: A system and method for reducing performance penalties of a host that is supplying a host memory buffer (HMB) for use by a storage device. The method may include modeling desired HMB access timing by the storage device in an initial offline analysis for multiple classes of workloads, periodically updating the access timing data stored in the storage device based on actual use and using the current HMB access timing information to modify storage device access to the HMB on the host. The system may include a storage device controller that quantifies different HMB access timing for different host workloads based on individual HMB regions.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.

Abstract: A non-volatile storage apparatus comprises a non-volatile storage and a control circuit connected to the non-volatile storage. The non-volatile storage structure is organized into multiple partitions. Each partition is preassigned to a different data shaping level. Data to be stored in the non-volatile storage is shaped based on its entropy. The control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data.