Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.

Abstract: A system and method for optimization of non-volatile storage operational parameters is provided. The method may utilize a crowdsourcing server to gather performance data for multiple storage devices connected to respective remotely located host systems. The performance data may be transmitted at regular intervals or at predefined events and the crowdsourcing server may aggregate and determine improved operating parameters for each different type of storage device based on the data gathered for multiple instances of that type of storage device. The optimized operating parameters may be selected from pre-stored and pre-qualified operating parameter sets on the respective storage devices that the crowdsourcing server is aware of. The system includes a non-volatile memory and a controller that is configured to log performance data and transmit at least a portion of that logged data to the crowdsourcing server.

Abstract: Technology is described herein for learning parameters for a parameterized iterative message passing decoder, and to a corresponding parameterized iterative message passing decoder. Learning the parameters may adapt the decoder to statistical dependencies introduced by the specific code's graph. Taking into account the statistical dependencies may allow the code to be shorter and/or denser. Note that the statistical dependencies in the graph may be extremely complex. Machine learning may be used to learn the parameters. The parameters may be learned when decoding data stored in the memory device. Learning the parameters may adapt the decoder to properties of data stored in the memory device, physical properties of the memory device, and/or patterns in host data.

Abstract: Systems and methods are described for predicting an endurance of groups of memory cells within a memory device, based on current characteristics of the cells. The endurance may be predicted by processing historical information regarding operation of memory devices according to a machine learning algorithm, such as a neural network algorithm, to generate correlation information between characteristics of groups of memory calls at a first time and an endurance metric at a second time. The correlation information can be applied to current characteristics of a group of memory cells to predict a future endurance of that group. Operating parameters of a memory device may be modified at a per-block level based on predicted block endurances to increase the speed of a device, the longevity of a device, or both.

Abstract: Apparatuses, systems, and methods are disclosed for dynamic read operations. An on-die controller monitors one or more read statistics during a read operation for data of a non-volatile memory die. An on-die controller determines whether one or more read statistics satisfy a threshold for a read operation. An on-die controller dynamically modifies a read operation based on determining that one or more read statistics fail to satisfy a threshold.

Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Abstract: A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.

Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.

Abstract: Head mountable camera devices, systems, and methods are disclosed.

Abstract: A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.

Abstract: A storage system and method for providing gray levels of read security are provided. In one embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. The controller is configured to perform a test of a security feature of the storage system; and in response to failure of the test of the security feature of the storage system, degrade a subsequent read of a set of locations in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.

Abstract: A device includes a memory, an error correction code (ECC) decoder, and an ECC input adjuster. The ECC decoder is configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters. The ECC input adjuster is configured to adjust one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous.

Abstract: A storage system and method for providing gray levels of read security are provided. In one embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. The controller is configured to perform a test of a security feature of the storage system; and in response to failure of the test of the security feature of the storage system, degrade a subsequent read of a set of locations in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.

Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.