Patents by Inventor Armin Willmeroth

Armin Willmeroth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193796
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Patent number: 10971582
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Patent number: 10950691
    Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Giulio Fragiacomo, Bjoern Fischer, Rene Mente, Armin Willmeroth
  • Publication number: 20210020626
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: Armin Willmeroth, Franz Hirler, Peter Irsigler
  • Patent number: 10833066
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Peter Irsigler
  • Publication number: 20200295202
    Abstract: A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 17, 2020
    Inventors: Ahmed Mahmoud, Rolf Weis, Armin Willmeroth
  • Publication number: 20200044019
    Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: Franz Hirler, Wolfgang Jantscher, Yann Ruet, Armin Willmeroth
  • Publication number: 20200044020
    Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Giulio Fragiacomo, Bjoern Fischer, Rene Mente, Armin Willmeroth
  • Publication number: 20200027949
    Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
  • Patent number: 10516065
    Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 24, 2019
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Philipp Seng, Armin Willmeroth
  • Patent number: 10490656
    Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Uwe Wahl
  • Patent number: 10475880
    Abstract: A transistor device includes drain, source and gate nodes, a plurality of drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Giulio Fragiacomo, Armin Willmeroth, Bjoern Fischer, Rene Mente
  • Patent number: 10468479
    Abstract: A semiconductor device includes a semiconductor body, which includes transistor cells and a drift zone between a drain layer and the transistor cells. The drift zone includes a compensation structure. Above a depletion voltage a first output charge gradient obtained by increasing a drain-to-source voltage from the depletion voltage to a maximum drain-to-source voltage deviates by less than 5% from a second output charge gradient obtained by decreasing the drain-to-source voltage from the maximum drain-to-source voltage to the depletion voltage. At the depletion voltage the first output charge gradient exhibits a maximum curvature.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
  • Patent number: 10276655
    Abstract: A semiconductor device includes a plurality of compensation regions of a first conductivity type arranged in a semiconductor substrate. The semiconductor device further includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement. The drift region has a second conductivity type. The drift region portions and the compensation regions are arranged alternatingly. At least portions of a border of a depletion region occurring in a static blocking state of the vertical electrical element arrangement are located within the drift region portions at a depth of less than a depth of at least a subset of the compensation regions.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Armin Willmeroth
  • Publication number: 20190019887
    Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 17, 2019
    Inventors: Armin Willmeroth, Franz Hirler, Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Uwe Wahl
  • Publication number: 20180374919
    Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 27, 2018
    Inventors: Armin Tilke, Hans Weber, Christian Fachmann, Roman Knoefler, Gabor Mezoesi, Manfred Pippan, Thomas Rupp, Michael Treu, Armin Willmeroth
  • Patent number: 10128367
    Abstract: Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Ahmed Mahmoud, Enrique Vecino Vazquez
  • Patent number: 10014367
    Abstract: A semiconductor device includes a transistor cell area with active transistor cells including source zones electrically connected to a first load electrode. The source zones have a first conductivity type. An edge area surrounds the active transistor cell area and includes an edge construction that includes straight sections and a corner section connecting neighboring straight sections. A second dopant ratio between a mean concentration of dopants of a complementary second conductivity type and a mean concentration of dopants of the first conductivity type in the corner section exceeds a first dopant ratio between a mean concentration of dopants of the second conductivity type and a mean concentration of dopants of the first conductivity type in the straight sections by at least 0.2% in relation to the first dopant ratio.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 3, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Armin Willmeroth
  • Patent number: 9972619
    Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 15, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Rolf Weis, Franz Hirler, Martin Feldtkeller, Gerald Deboy, Matthias Stecher, Armin Willmeroth
  • Patent number: RE47710
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth