Abstract: In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4, which are arranged alternately, form a voltage holding area. The first terminal 101 is connected to the p-type regions through wiring, and the second terminal 102 is connected to the n-type regions 2. Also, the p-type region is formed to cover the bottom comers of a gate polycrystalline silicon layer 8.

Abstract: An interference filter transmission wavelength scanning photometer wherein the angle of inclination of an interference filter (3) is periodically varied, the wavelength of the light to be transmitted is modulated with the periodical variation centered at the maximum absorption wavelength of the interesting component, the variation of the intensity of the light transmitted through a sample is extracted by an infrared sensor (11) as an electrical signal. The time between the rise and fall zero cross points of the AC component of the electric signal is determined by a microprocessor (16), the ratio (T−2T1)/T.

Abstract: A sensor with built-in circuits can be improved in the stability of the operation or characteristics. A circuit region and a sensor region are covered by a passivation film. The sensor region is partially covered by the passivation film. The sensor region and circuit region are protected by the passivation film, and an effect of the passivation film on the mechanical displacement of a diaphragm portion can be alleviated so that the sensor with built-in circuits may be improved in the stability of the operation or characteristics.

Abstract: The present invention provides a semiconductor integrated circuit device comprising a digital circuit and an analog circuit on a common substrate wherein a substrate effect constant of the analog circuit is at least less than a substrate effect constant of the digital circuit and wherein the analog circuit further comprises a P type polysilicon gate electrode for a nMOSFET and a N type polysilicon gate electrode for a pMOSFET.

Abstract: A MOS field effect transistor. A field relaxation layer of a gate overlap structure is disposed in contact with a drain region for the purpose of relaxation of the electric field by increasing a distance between the field relaxation layer and a high-density layer. The electric field relaxation can further be promoted because the equipotential lines are bent by a gate insulation film. A punch-through stopper layer of a gate overlap structure is disposed in contact with a source region for suppressing spreading of a depletion layer toward the source region. The length of a gate electrode can be realized in a miniaturized size.

Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor 11d in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 11a to 11d can increase the withstand voltage of a semiconductor integrated circuit.

Abstract: In an interface device in which by means of a buried insulation film 412 and a region insulation portion 410 an SOI substrate 414 is divided into a semiconductor support substrate region 411, a controller side region 407 and a network side region 408 and a part of isolator circuits 405 and 406 making use of a static capacitance are formed in the network side region 408, the semiconductor support substrate region 411 and the network side region 408 are connected to a network power source to always keep these regions at a same potential, thereby, an interface device using a dielectric isolation substrate which suppresses erroneous operations due to noises and characteristic deterioration, and a system using the same are provided.

Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor lid in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 1a to 11d can increase the withstand voltage of a semiconductor integrated circuit.

Abstract: An endless belt in which a fibrous material is dispersed in a substantially uniform manner all over an endless elastic body layer is provided. A non-woven tape is impregnated with a polyurethane elastomer material liquid and wound and layered on a supporting belt, and then, after curing the polyurethane elastomer material liquid to form an elastic body, it is removed from supporting belt.

Abstract: In the resin roll 5 for calendering a magnetic recording medium, a surface portion 3a of a thermosetting resin outer layer 3 has high storage elastic modulus (E′) of 5×1010 to 5×1011 dyn/cm2 at a temperature of 50° to 150° C. at a frequency of 10 hertz (Hz). At the surface portion of the thermosetting resin outer layer, the expression representing the relation between storage elastic modulus (E′) and the Poisson's ratio (&ngr;) is within the following range, under the same conditions: 2×10−12 cm2/dyn<(1−&ngr;2)/E′<2×10−11 cm2/dyn.

Abstract: According to the present invention, there is provided an N-type insulated gate field effect transistor using an SOI substrate of which Si layer as a device formation area is N-type. The SOI substrate provided as the device formation area has the N-type semiconductor region, which has an impurity concentration higher than the impurity concentration of the device formation area, formed so that the N-type semiconductor region is contacted to a part of a gate insulating film and a field silicon oxide film formed between a source electrode and a drain electrode, and extends to be contacted to the N-type semiconductor diffusion layer contacted to the drain electrode. According to the above arrangement, the on-state breakdown can be remarkably improved.

Abstract: In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4 which are arranged alternately and adjacently form a voltage holding area, said first terminal 101 is connected to said p-type regions through wiring, and said second terminal 102 is connected to said n-type regions 2. Also, said p-type region is formed to cover the bottom corners of a gate polycrystalline silicon layer 8.

Abstract: When a first bi-wiring speaker is connected to output terminals 5A and 5B and a second bi-wiring speaker is connected to output terminals 5D and 5E, and further a two-channel stereo reproduction is performed, a signal 3L for a L channel outputted from a decoder 2 is amplified by amplifiers 4A and 4B in parallel to be given to the first bi-wiring speaker in a bi-wiring connecting manner and a signal 3R for a R channel outputted from the decoder 2 is amplified by amplifiers 4C and 4D in parallel and given to the second bi-wiring speaker in a bi-wiring connecting manner. At this time, a gain corrector 7 equalizes a gain which an output signal of the amplifier 4A has with respect to the signal 3L for the L channel with a gain which an output signal of the amplifier 4B has with respect to the signal 3L for the L channel.

Abstract: In a resin roll 5 for calendering a magnetic recording medium, a surface portion 3a of a thermosetting resin outer layer 3 has high storage elastic modulus (E') of 5.times.10.sup.10 to 5.times.10.sup.11 dyn/cm.sup.2 at a temperature of 50 to 150.degree. C. at a frequency of 10 hertz (Hz). At the surface portion of the thermosetting resin outer layer, the expression representing the relation between storage elastic modulus (E') and the Poisson's ratio (.nu.) is within the following range, under the same conditions:2.times.10.sup.-12 cm.sup.2 /dyn<(1-.nu..sup.2)/E'<2.times.10.sup.-11 cm.sup.

Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

Abstract: In a resin roll 5 for calendering a magnetic recording medium, a surface portion 3a of a thermosetting resin outer layer 3 has high storage elastic modulus (E') of 5.times.10.sup.10 to 5.times.10.sup.11 dyn/cm.sup.2 at a temperature of 50.degree. to 150.degree. C. at a frequency of 10 hertz (Hz). At the surface portion of the thermosetting resin outer layer, the expression representing the relation between storage elastic modulus (E') and the Poisson's ratio (.nu.) is within the following range, under the same conditions:2.times.10.sup.-12 cm.sup.2 /dyn<(1-.nu..sup.2)/E'<2.times.10.sup.-11 cm.sup.

Abstract: A process for producing a hard roll for use as an elastic roll for making paper calendering by casting a liquid thermosetting resin material into a space between a metal roll core and an outer mold, and thereafter heating the resin material from outside to cure a major portion of the material and to form an outer layer resin intermediate body, while cooling the resin material from the roll core side to leave a viscount liquid resin material layer inside the intermediate body. The intermediate body is subsequently cooled from outside the outer mold to contract the body, allowing an excess of the liquid material to be forced out upwardly with the contraction of the body. The material is thereafter heated from the roll core side to cure the remaining viscous liquid resin material. The hard roll can be produced without cracking due to the reaction contraction and thermal shrinkage of the thermosetting resin. The roll is usable without cracking in its surface hardness despite the influence of heat.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.