Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10263074
    Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Publication number: 20190103486
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Application
    Filed: July 2, 2016
    Publication date: April 4, 2019
    Inventors: Willy RACHMADY, Van H. LE, Matthew V. METZ, Benjamin CHU-KUNG, Ashish AGRAWAL, Jack T. KAVALIEROS
  • Patent number: 10249490
    Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
  • Patent number: 10249742
    Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Gilbert Dewey, Benjamin Chu-Kung, Ashish Agrawal, Matthew V. Metz, Willy Rachmady, Marc C. French, Jack T. Kavalieros, Rafael Rios, Seiyon Kim, Seung Hoon Sung, Sanaz K. Gardner, James M. Powers, Sherry R. Taft
  • Publication number: 20190088747
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 21, 2019
    Inventors: Niti GOEL, Gilbert DEWEY, Niloy MUKHERJEE, Matthew V. METZ, Marko RADOSAVLIJEVIC, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
  • Patent number: 10236369
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • Patent number: 10229991
    Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Marko Radosavljevic, Seung Hoon Sung, Benjamin Chu-Kung, Robert S. Chau
  • Patent number: 10224399
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Publication number: 20190058053
    Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
    Type: Application
    Filed: December 21, 2015
    Publication date: February 21, 2019
    Inventors: Gilbert DEWEY, Jack T. KAVALIEROS, Willy RACHMADY, Matthew V. METZ, Van H. LE, Seiyon KIM, Benjamin CHU-KUNG
  • Patent number: 10204989
    Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Sherry R. Taft, Van H. Le, Sansaptak Dasgupta, Seung Hoon Sung, Sanaz K. Gardner, Matthew V. Metz, Marko Radosavljevic, Han Wui Then
  • Publication number: 20190030492
    Abstract: Membranes of the present disclosure possess very thin barrier layers, with high selectivity, high throughput, low fouling, and are long lasting. The membranes include graphene and/or graphene oxide barrier layers on a nanofibrous supporting scaffold. Methods for forming these membranes, as well as uses thereof, are also provided. In embodiments, an article of the present disclosure includes a nanofibrous scaffold; at least a first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof on at least a portion of a surface of the nanofibrous scaffold; an additive such as crosslinking agents and/or particles on an outer surface of the at least first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Hongyang Ma, Zhe Wang
  • Publication number: 20190035921
    Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.
    Type: Application
    Filed: March 31, 2016
    Publication date: January 31, 2019
    Inventors: Cheng-Ying Huang, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Benjamin Chu-Kung, Gilbert Dewey, Rafael Rios
  • Patent number: 10186581
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 10181518
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 10177249
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Publication number: 20180374928
    Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 24, 2015
    Publication date: December 27, 2018
    Inventors: GILBERT DEWEY, ASHISH AGRAWAL, BENJAMIN CHU-KUNG, VAN H. LE, MATTHEW V. METZ, WILLY RACHMADY, JACK T. KAVALIEROS, RAFAEL RIOS
  • Publication number: 20180366587
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 20, 2018
    Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
  • Publication number: 20180331195
    Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.
    Type: Application
    Filed: December 24, 2015
    Publication date: November 15, 2018
    Inventors: Willy RACHMADY, Matthew V. METZ, Benjamin CHU-KUNG, Van H. LE, Gilbert DEWEY, Ashish AGRAWAL, Jack T. KAVALIEROS
  • Publication number: 20180331224
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Application
    Filed: July 19, 2018
    Publication date: November 15, 2018
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung, Sanaz Gardner, Ravi Pillarisetty
  • Patent number: 10112150
    Abstract: Membranes of the present disclosure possess very thin barrier layers, with high selectivity, high throughput, low fouling, and are long lasting. The membranes include graphene and/or graphene oxide barrier layers on a nanofibrous supporting scaffold. Methods for forming these membranes, as well as uses thereof, are also provided. In embodiments, an article of the present disclosure includes a nanofibrous scaffold; at least a first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof on at least a portion of a surface of the nanofibrous scaffold; an additive such as crosslinking agents and/or particles on an outer surface of the at least first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 30, 2018
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Hongyang Ma, Zhe Wang