Patents by Inventor Bernard Aspar

Bernard Aspar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210058058
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 25, 2021
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 10826459
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: November 3, 2020
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Publication number: 20200280298
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Publication number: 20190372243
    Abstract: A structure for a for radiofrequency application applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.
    Type: Application
    Filed: January 29, 2018
    Publication date: December 5, 2019
    Inventors: Eric Desbonnets, Bernard Aspar
  • Publication number: 20180159498
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Application
    Filed: June 9, 2016
    Publication date: June 7, 2018
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9511996
    Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 6, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9481566
    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 1, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20150210540
    Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
    Type: Application
    Filed: July 8, 2013
    Publication date: July 30, 2015
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20150191344
    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
    Type: Application
    Filed: July 8, 2013
    Publication date: July 9, 2015
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20150179520
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Application
    Filed: July 8, 2013
    Publication date: June 25, 2015
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 8722515
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: May 13, 2014
    Assignee: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8679946
    Abstract: A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 25, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 8628674
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: January 14, 2014
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Soitec
    Inventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
  • Patent number: 8609514
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 17, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Publication number: 20130323861
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 5, 2013
    Applicant: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8575010
    Abstract: The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Alexis Drouin, Bernard Aspar, Christophe Desrumaux, Olivier Ledoux, Christophe Figuet
  • Publication number: 20130273713
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 17, 2013
    Inventors: Hubert MORICEAU, Michel BRUEL, Bernard ASPAR, Christophe MALEVILLE
  • Patent number: 8530334
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: September 10, 2013
    Assignee: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8481409
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: July 9, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre