Patents by Inventor Bernard Aspar
Bernard Aspar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8628674Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.Type: GrantFiled: November 20, 2012Date of Patent: January 14, 2014Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, SoitecInventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
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Patent number: 8609514Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.Type: GrantFiled: May 24, 2013Date of Patent: December 17, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
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Publication number: 20130323861Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.Type: ApplicationFiled: August 2, 2013Publication date: December 5, 2013Applicant: SoitecInventors: Chrystelle Lagahe, Bernard Aspar
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Patent number: 8575010Abstract: The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.Type: GrantFiled: February 26, 2009Date of Patent: November 5, 2013Assignee: SoitecInventors: Alexis Drouin, Bernard Aspar, Christophe Desrumaux, Olivier Ledoux, Christophe Figuet
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Publication number: 20130273713Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.Type: ApplicationFiled: May 24, 2013Publication date: October 17, 2013Inventors: Hubert MORICEAU, Michel BRUEL, Bernard ASPAR, Christophe MALEVILLE
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Patent number: 8530334Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.Type: GrantFiled: January 16, 2009Date of Patent: September 10, 2013Assignee: SoitecInventors: Chrystelle Lagahe, Bernard Aspar
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Patent number: 8481409Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.Type: GrantFiled: September 23, 2005Date of Patent: July 9, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
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Patent number: 8475693Abstract: This invention provides composite semiconductor substrates and methods for fabricating such substrates. The composite structures include a semiconductor substrate, a semiconductor superstrate and an intermediate layer interposed between the substrate and the superstrate that comprises a material that undergoes a structural transformation when subject to a suitable heat treatment. The methods provide such a heat treatment so that the intermediate layer becomes spongy or porous, being filled with numerous micro-bubbles or micro-cavities containing a gaseous phase. The composite semiconductor substrates with structurally-transformed intermediate layers have numerous applications.Type: GrantFiled: June 16, 2011Date of Patent: July 2, 2013Assignee: SoitecInventors: Michel Bruel, Bernard Aspar, Chrystelle Lagahe-Blanchard
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Patent number: 8470712Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.Type: GrantFiled: December 23, 2010Date of Patent: June 25, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
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Publication number: 20130012024Abstract: A process for making cavities in a multilayer structure by providing a multilayer structure that includes a surface layer, a planar support substrate and a buried layer between the layer and the support substrate, wherein the buried layer comprises areas of first and second materials with the first material having a higher etching rate than the second material; producing an opening in the surface layer that extends to the area(s) of the first material of the buried layer; and etching the first material to form at least one cavity in the buried layer.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: SOITECInventor: Bernard Aspar
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Patent number: 8329048Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.Type: GrantFiled: December 22, 2005Date of Patent: December 11, 2012Assignees: Commissariat a l'Energie Atomique, S.O.I. TEC Silicon On Insulator Technologies of Chemin des FranquesInventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
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Patent number: 8298915Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.Type: GrantFiled: December 22, 2005Date of Patent: October 30, 2012Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventor: Bernard Aspar
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Patent number: 8268703Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.Type: GrantFiled: July 13, 2007Date of Patent: September 18, 2012Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
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Patent number: 8232130Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.Type: GrantFiled: August 21, 2008Date of Patent: July 31, 2012Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Marcel Broekaart, Bernard Aspar, Thierry Barge, Chrystelle L. Blanchard
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Patent number: 8193069Abstract: The invention relates to a method of producing a stacked structure. The inventive method comprises the following steps consisting in: a) using a first plate (1) which is, for example, made from silicon, and a second plate (5) which is also, for example, made from silicon, such that at least one of said first (1) and second (5) plates has, at least in part, a surface (2; 7) that cannot bond to the other plate; b) providing a surface layer (3; 8), which is, for example, made from silicon oxide, on at least one part of the surface (2) of the first plate and/or the surface (7) of the second plate (5); and c) bonding the two plates (1; 5) to one another. The aforementioned bonding incompatibility can, for example, result from the physicochemical nature of the surface or of a coating applied thereto, or from a roughness value (r?2, r?7) which is greater than a predetermined threshold. The invention also relates to a stacked structure produced using the inventive method.Type: GrantFiled: July 15, 2004Date of Patent: June 5, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Bernard Aspar, Jacques Margail
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Publication number: 20120133028Abstract: A semiconductor structure includes a thin semiconductor layer fixed on an applicator or flexible support, the thin layer having an exposed surface characterized by fractured solid bridges spaced apart by cavities. A method of producing the thin layer of semiconductor material includes implanting ions into the semiconductor wafer to define a reference plane, where the ion dose is above a minimum dose, but below a critical dose so as to avoid degrading the wafer surface. The method further includes applying a thermal treatment to define a layer of microcavities and applying stress to free the thin layer from the wafer.Type: ApplicationFiled: November 28, 2011Publication date: May 31, 2012Inventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
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Patent number: 8158487Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.Type: GrantFiled: January 21, 2011Date of Patent: April 17, 2012Assignee: SoitecInventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
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Patent number: 8101503Abstract: A semiconductor structure includes a thin semiconductor layer fixed on an applicator or flexible support, the thin layer having an exposed surface characterized by fractured solid bridges spaced apart by cavities. A method of producing the thin layer of semiconductor material includes implanting ions into the semiconductor wafer to define a reference plane, where the ion dose is above a minimum dose, but below a critical dose so as to avoid degrading the wafer surface. The method further includes applying a thermal treatment to define a layer of microcavities and applying stress to free the thin layer from the wafer.Type: GrantFiled: December 12, 2008Date of Patent: January 24, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
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Patent number: 8044465Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.Type: GrantFiled: March 24, 2010Date of Patent: October 25, 2011Assignee: S.O.I.TEC Solicon On Insulator TechnologiesInventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
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Publication number: 20110250416Abstract: This invention provides composite semiconductor substrates and methods for fabricating such substrates. The composite structures include a semiconductor substrate, a semiconductor superstrate and an intermediate layer interposed between the substrate and the superstrate that comprises a material that undergoes a structural transformation When subject to a suitable heat treatment. The methods provide such a heat treatment so that the intermediate layer becomes spongy or porous, being filled with numerous micro-bubbles or micro-cavities containing a gaseous phase. The composite semiconductor substrates with structurally-transformed intermediate layers have numerous applications.Type: ApplicationFiled: June 16, 2011Publication date: October 13, 2011Inventors: Michel Bruel, Bernard Aspar, Chrystelle Lagahe-Blanchard