Patents by Inventor Bernard Aspar

Bernard Aspar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7498245
    Abstract: This invention relates to a substrate (1) weakened by the presence of a micro-cavities zone, the micro-cavities zone (4?) delimiting a thin layer (5) with one face (2) of the substrate (1), some or all of the gaseous species having been eliminated from the micro-cavities (4?). The invention also relates to a process for the production of such a substrate.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 3, 2009
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Bernard Aspar, Chrystelle Lagahe, Olivier Rayssac, Bruno Ghyselen
  • Patent number: 7498234
    Abstract: The invention relates to a method of producing a thin layer of semiconductor material including: a step of implanting ions through a flat face (2) of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face, a thermal treatment step in order to achieve coalescence of the microcavities possibly, a step of creating at least one electronic component (5) in the thin layer (6), a separation step of separating the thin layer (6) from the rest (7) of the wafer.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: March 3, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
  • Patent number: 7494897
    Abstract: The inventive method includes a preparation step during which the substrate is covered with a layer, a pressing step in which a mould including a pattern of recesses and protrusions is pressed into part of the thickness of the aforementioned layer, at least one etching step in which the layer is etched until parts of the surface of the substrate have been stripped, and a substrate etching step whereby the substrate is etched using an etching pattern which is defined from the mould pattern. The preparation step includes a sub-step consisting of the formation of a lower sub-layer of curable material, a step involving the curing of said layer and a sub-step including the formation of an outer sub-layer which is adjacent to the cured sub-layer. Moreover, during the pressing step, the above-mentioned protrusions in the mould penetrate the outer sub-layer until contact is reached with the cured sub-layer.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 24, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Franck Fournel, Hubert Moriceau, Bernard Aspar, Marc Zussy
  • Publication number: 20080254596
    Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 16, 2008
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Publication number: 20080176381
    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 24, 2008
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Publication number: 20080176382
    Abstract: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining an external oxide surface on the first semiconductor substrate and a buried oxide-semiconductor interface below the oxide surface, so that the buried oxide surface has a roughness R2 that is less than R1. The method also includes assembling the oxide surface of the first semiconductor substrate with a second substrate. The invention also provides a component formed according to the method of the invention.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 24, 2008
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Publication number: 20080128868
    Abstract: The invention relates to a method for producing a semi-conductor structure consisting in a) producing at least one part of a circuit in or on a surface layer (2) of a substrate, which comprises said surface layer (2), a layer (4) buried under said surface layer and an underlying layer (6) used in the form of a first support, b) transferring said substrate to a handle substrate (20) and in removing the first support (6), c) forming a bonding layer (12) on said electrically conductive or a grounding plane forming layer (14) and e) transferring the assembly to a second support (30) and in removing the handle substrate (20).
    Type: Application
    Filed: December 22, 2005
    Publication date: June 5, 2008
    Applicant: TRACIT TECHNOLOGIES
    Inventor: Bernard Aspar
  • Patent number: 7368030
    Abstract: The present invention relates to an intermediate suction support. The support has at least one suction surface (62) intended to receive a first face of at least one substrate comprising an embrittled layer, a film thus being defined between the first face of the substrate and the embrittled layer, the suction surface (62) of the intermediate support being the face with at least one suction element (63) comprising suction means provided so that, when the embrittled layer is submitted to a treatment leading to the separation of the film from the rest of the substrate, the film can be recuperated. Application to the production of a thin film structure.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: May 6, 2008
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Claude Jaussaud, Michel Bruel, Bernard Aspar
  • Publication number: 20080036039
    Abstract: The invention relates to a process for making a semiconducting structure composed of a surface layer (2), at least one buried layer (4) and a support, comprising: —a first step to make a first layer (44) made of a first material on a first support, and at least one area (26, 28) in this first layer made of a second material with an etching rate greater than the etching rate of the first material, —a second step for the formation of the surface layer (2), by assembly of the structure on a second support, and thinning of at least one of the two supports.
    Type: Application
    Filed: September 27, 2005
    Publication date: February 14, 2008
    Applicant: TRACIT TECHNOLOGIES
    Inventor: Bernard Aspar
  • Publication number: 20070232025
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Application
    Filed: May 11, 2007
    Publication date: October 4, 2007
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Patent number: 7264996
    Abstract: This invention relates to a method for separating at least two wafers (1, 2) bonded together to form a stacked structure. At least one bending force is applied to all or part of the stacked structure to separate the stacked structure into two parts along a required separation plane. Application particularly for producing a thin semiconducting layer.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: September 4, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Frank Fournel, Bernard Aspar
  • Publication number: 20070200144
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard ASPAR, Chrystelle Lagahe-Blanchard
  • Patent number: 7258743
    Abstract: This invention relates to a process for controlling the orientation of secondary structures (A1, A2) with at least a crystalline part during the transfer of secondary structures from a primary structure (A) on which the secondary structures have an initial crystalline orientation identical to the orientation of the primary structure, onto at least one support structure (B), the process comprising: a) the formation of at least one orientation mark (Va, Va1, Va2) when the secondary structures are fixed to the primary structure (A), the mark having an arbitrary orientation with respect to the said initial crystalline orientation, but identical for each secondary structure, and b) when a set of secondary structures is transferred onto at least one support structure (B), an arrangement of the secondary structures so that their orientation marks can be oriented in a controlled manner.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 21, 2007
    Assignee: Commissariat A L'Energie Atomique
    Inventors: Franck Fournel, Bernard Aspar, Hubert Moriceau
  • Patent number: 7238598
    Abstract: A method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-cavities and/or micro-bubbles, a thin layer of semiconductor material thus being delimited between the embrittled layer and one face of the substrate, thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face of the substrate in the form of blisters but without generating exfoliations of the thin layer during this step and during the continuation of the method, epitaxy of semiconductor material on said face of the substrate to provide at least one epitaxial layer on said thin film.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: July 3, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Chrystelle Lagahe, Bernard Aspar, Aurélie Beaumont
  • Patent number: 7229899
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: June 12, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Patent number: 7205211
    Abstract: This invention relates to a method for making a thin layer starting from a wafer comprising a front face with a given relief, and a back face, comprising steps consisting of: a) obtaining a support handle with a face acting as a bonding face; b) preparing the front face of the wafer, this preparation including incomplete planarisation of the front face of the wafer, to obtain a bonding energy E0 between a first value corresponding to the minimum bonding energy compatible with the later thinning step, and a second value corresponding to the maximum bonding energy compatible with the subsequent desolidarisation operation, the bonding energy E0 being such that E0=?.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: April 17, 2007
    Assignee: Commisariat l'Energie Atomique
    Inventors: Bernard Aspar, Marc Zussy, Jean-Frédéric Clerc
  • Publication number: 20070072393
    Abstract: A method for assembling a first and a second wafer of material, including routing at least the first wafer and assembling the first and second wafer.
    Type: Application
    Filed: October 14, 2004
    Publication date: March 29, 2007
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Publication number: 20070037363
    Abstract: The invention concerns a method for making a thin film, which consists in creating a brittle zone embedded by implantation of a chemical species in a substrate, so as to be able subsequently to provoke a fracture of the substrate along said brittle zone to separate therefrom said thin film. The invention is characterized in that the manufacturing method comprises in particular the following steps: a) a first implantation in the substrate at a first depth of a first chemical species; b) implanting at least one second chemical species in the substrate, at a second depth different from said first depth, and at a concentration higher than the concentration of the first species, where the at least a second chemical species is less efficient than the first chemical species for embrittling the substrate; c) diffusing at least part of said secondary species to the vicinity of the first depth; and d) initiating a fracture along the first depth.
    Type: Application
    Filed: May 27, 2004
    Publication date: February 15, 2007
    Inventors: Bernard Aspar, Christelle Lagahe, Nicolas Sousbie, Jean-Francois Michaud
  • Publication number: 20060281212
    Abstract: The invention relates to a method of producing a stacked structure. The inventive method comprises the following steps consisting in: a) using a first plate (1) which is, for example, made from silicon, and a second plate (5) which is also, for example, made from silicon, such that at least one of said first (1) and second (5) plates has, at least in part, a surface (2; 7) that cannot bond to the other plate; b) providing a surface layer (3; 8), which is, for example, made from silicon oxide, on at least one part of the surface (2) of the first plate and/or the surface (7) of the second plate (5); and c) bonding the two plates (1; 5) to one another. The aforementioned bonding incompatibility can, for example, result from the physicochemical nature of the surface or of a coating applied thereto, or from a roughness value (r?2, r?7) which is greater than a predetermined threshold. The invention also relates to a stacked structure produced using the inventive method.
    Type: Application
    Filed: July 15, 2004
    Publication date: December 14, 2006
    Inventors: Hubert Moriceau, Bernard Aspar, Jacques Margail
  • Publication number: 20060191627
    Abstract: A process for cutting out a block of material (10) comprising the following stages: (a) the formation in the block of a buried zone (12), embrittled by at least one stage of ion introduction, the buried zone defining at least one superficial part (14) of the block, (b) the formation at the level of the embrittled zone of at least one separation initiator (30, 36) by the use of a first means of separation chosen from amongst the insertion of a tool, the injection of a fluid, a thermal treatment and/or implantation of ions of an ionic nature different from that introduced during the preceding stage, and (c) the separation at the level of the embrittled zone of the superficial part (14) of the block from a remaining part (16), called the mass part, from the separation initiator (30, 36) by the use of a second means, different from the first means of separation and chosen from among a thermal treatment and/or the application of mechanical forces acting between the superficial part and the embrittled zone.
    Type: Application
    Filed: March 10, 2006
    Publication date: August 31, 2006
    Inventors: Bernard Aspar, Chrystelle Lagache