Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.

Abstract: One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam.

Abstract: A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.

Abstract: A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step.

Abstract: A system for characterizing an etch process via scatterometry based real time imaging is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time etch image to characterize the progress of the etching and, in one example, produces suggested adaptations to the etch process.

Abstract: The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surface of an integrated circuit wafer, and comparing the reference signal and the reflection signal to locate absorption bands, the absorption band being indicative of a process end point.

Abstract: The disclosure describes an exemplary method of using a dual layer feature on a mask in an integrated circuit fabrication process to provide for use of the mask at multiple wavelengths. This method can include providing a dual layer feature over a mask, where the dual layer feature is configured with layers of selected thicknesses which allow the mask to be used at multiple wavelengths; and subjecting the dual layer feature and the mask to a beam at one of the multiple wavelengths.

Abstract: The present invention is directed to a system and a method for calibrating a lithography stepper system. The system includes a lithography stepper system, measurement system such as a scatterometry system, and a processor for correlating an ideal “golden standard” characterization signature to a test structure characterization data set, based on a plurality of focus and exposure conditions.

Abstract: One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.

Abstract: A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.

Abstract: One aspect of the present invention relates to a system for dissipating electrostatic charge on a mask plate structure containing the mask plate structure containing a substrate, a chromium layer over the substrate, and a conductive polymer over the chromium layer; a conductive structure coupled to the mask plate structure which allows accumulated electrostatic charge to flow from the mask plate structure; a conductive path between the conductive structure and a ground, wherein the conductive path inacludes a switch controlled by a controller; and a detector coupled to the controller for signaling the controller when the accumulation of electrostatic charge is detected.

Abstract: In one embodiment, the present invention relates to a method of processing a photoresist on a semiconductor structure, involving the steps of exposing and developing the photoresist; evaluating the exposed and developed photoresist to determine if negative charges exist thereon; contacting the exposed and developed photoresist with a positive ion carrier thereby reducing any negative charges thereon; and evaluating the exposed and developed photoresist with an electron beam.

Abstract: A measuring system and apparatus is provided in which a scanning probe microscope includes a high resolution optical sensor adapted to view a portion of a workpiece beneath the scanning probe tip. Also provided is a scanning tip assembly with a cantilever/tip assembly and an optical sensor associated with the cantilever assembly. In one embodiment, the optical sensor comprises a charge coupled device or other solid state camera associated with the cantilever and/or the tip. In addition, a scanning tip assembly is provided for a scanning probe microscope having an optical fiber adapted to receive reflected light from the at least a portion of the workpiece. Also provided is a measuring apparatus comprising a scanning probe microscope having an optical fiber adapted to receive reflected light from a feature of a workpiece, and an optical processor connected to the optical fiber to provided a visual image based on the reflected light from the feature of the workpiece.

Abstract: The present invention provides lithographic systems and lithographic processes in which conditions affecting critical dimensions are controlled based on a latent image signature. The latent image signature characterizes the latent pattern present in a resist coating after selective exposure of the resist to actinic radiation. The latent image signature is determined from the full latent pattern within a region of the resist. Conditions for subsequent processing steps (feed forward control) and/or prior processing steps (feed back control) to produce desired critical dimensions are determined from the latent image signature. In another aspect of the invention the latent pattern is logically divided into a plurality of regions. Within each region, a characteristic of the latent pattern is analyzed to determine conditions to apply to that region during previous and/or subsequent processing steps.

Abstract: An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first layer of material according to the photoresist pattern to form material features; oxidizing exposed portions of the material features where the material features are made of a material which expands during oxidation; and etching the second layer of material according to the material features which have expanded as a result of oxidation. Advantageously, the expansion of the material features results in a smaller distance between material features than the distance between photoresist features.

Abstract: The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.

Abstract: The present invention relates to a method for mitigating formation of silicon grass. A silylation process is performed on a semiconductor structure, the structure including a photoresist layer, an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a portion of the photoresist layer.

Abstract: An exemplary method of forming an attenuating extreme ultraviolet (EUV) phase-shifting mask is described. This method can include providing a multi-layer mirror over an integrated circuit substrate or a mask blank, providing a buffer layer over the multi-layer mirror, providing a dual element material layer over the buffer layer, and selectively growing features on the integrated circuit substrate or mask blank using a photon assisted chemical vapor deposition (CVD) process when depositing the dual element layer.

Abstract: A system and method are disclosed for providing in-situ monitoring of thin film thickness, such as by employing a non-destructive optical measurement technique. The monitored film thickness may be employed to help achieve a desired feature film thickness and uniformity across a surface of a substrate. By monitoring film thickness during semiconductor processing, for example, one or more process control parameters may be adjusted to help achieve a desired film thickness and/or uniformity thereof.