Abstract: The present invention relates to systems and methods to regulate spacer deposition. The present invention employs a spacer deposition controller to control a spacer deposition component that deposits a spacer on a portion of a wafer. During and/or after spacer deposition, light can be directed at the spacer, wherein light reflected from the spacer is measured to determine parameters associated with the spacer deposition process. A processor operatively coupled to a measurement system and the spacer deposition controller utilizes the parameters to determine if the spacer process is proceeding in a suitable manner via comparing the measured parameters with stored acceptable parameters. If it is determined that the spacer deposition process is not proceeding as desired, then the measured parameters can be employed by the spacer deposition controller to adjust the spacer deposition process on the portion of the wafer and on subsequent portions of wafers.

Abstract: The present invention is directed to a method and a system for non-destructively, efficiently and accurately detecting asymmetry in the profile of a feature formed on a wafer during the process of semiconductor fabrication. The method encompasses directing a beam of light or radiation at a feature and detecting a reflected beam associated therewith. Data associated with the reflected beam is correlated with data associated with known feature profiles to ascertain profile characteristics associated with the feature of interest. Using the profile characteristics, an asymmetry of the feature is determined which is then used to generate feedback or feedforward process control data to compensate for or correct such asymmetry in subsequent processing.

Abstract: The present invention relates to systems and methods for increasing the hydrophobicity of patterned resists. In one embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin photoresist over a semiconductor substrate; irradiating the ultra-thin resist with electromagnetic radiation; developing the ultra-thin resist with a developer to form a patterned resist, the patterned resist having a surface with a first hydrophobicity; contacting the patterned resist with a transition solvent to provide the surface of the patterned resist with a second hydrophobicity, wherein the second hydrophobicity is greater than the first hydrophobicity and contact of the patterned resist with the transition is conducted between developing the ultra-thin resist and rinsing patterned resist; and rinsing the patterned resist having the second hydrophobicity with an aqueous solution.

Abstract: A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof.

Abstract: The present invention provides SEM calibration standards, and associated SEM systems and SEM calibration methods, that are self-cleaning with respect to electron beam deposited carbon. The calibration standards have coatings containing a transition metal oxide. The coatings facilitate oxidation of deposited carbon, whereby carbon buildup can be stopped or reversed. By providing a mechanism to mitigate carbon buildup, calibration standards provided by the present invention achieve high accuracy, high durability, and low cost.

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract: One aspect of the present invention relates to a method to facilitate formation of an oxide portion of an anti-reflective layer on a substrate. The method involves the steps of forming an oxidized portion of an anti-reflective coating over an anti-reflective layer disposed on the substrate; reflecting a beam of x-ray radiation at the oxidized portion; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the oxidized portion based on the measurement signal while the oxidized portion is being formed at the substrate.

Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and electrical resistance member(s) and/or electrical resistance entities located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a electrical resistance monitoring system that can read the wafer electrical resistance(s) from the electrical resistance member(s) and/or electrical resistance entities and that can determine wafer stress(es) based upon the electrical resistance(s) to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer electrical resistance(s) and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer electrical resistance(s) (e.g.

Abstract: A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.

Abstract: A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

Abstract: A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconductor structure has a thickness less than about 3000 Å, preferably less than about 2600 Å, and incorporates an adhesive layer that is preferably less than about 100 Å thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.

Abstract: The present invention provides a system and process for controlling the application of patterned resist coatings in an integrated circuit manufacturing process that employs multiple reticle patterns. One aspect of the invention relates to obtaining scatterometry measurements from a patterned resist and using the measurements to determine whether the correct reticle pattern was employed in forming the patterned resist. According to another aspect of the invention, the reticles are provided with grating patterns in addition to reticle patterns, whereby when the reticles are printed, gratings are formed in the resist. The gratings can be used, with scatterometry, to identify the reticle pattern. The reticles can be configured so that the gratings form in a non-functional portion of a wafer, such as a portion along a score line. Where it is, determined that the correct reticle pattern was not used, corrective action can be taken such as stripping the resist and reprocessing the affected wafers.

Abstract: One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.

Abstract: A system for regulating spacer deposition is provided. At least one spacer deposition component deposits spacer on a portion of a wafer. A spacer deposition controller regulates the at least one spacer deposition component. A system for directing light directs light to the at least one spacer and collects light reflected from the portion of the wafer. A measuring system measures thickness parameters associated with the deposited spacer. A processor is operatively coupled to the measuring system and the spacer deposition controller, wherein the processor receives the measured data from the measuring system, analyzes the measured data by comparing the measured data to stored acceptable spacer thickness values to determine necessary adjustments to the spacer deposition component via the spacer deposition controller to facilitate regulating spacer thickness on the portion of the wafer and on subsequent portions of wafers.

Abstract: The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.

Abstract: A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

Abstract: A system for regulating an exposure condition determining process is provided. The system includes one or more light sources, each light source directing light to one or more gratings exposed on one or more portions of a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is analyzed to determine whether exposure conditions should be adapted prior to exposing a pattern on the wafer. The measuring system provides grating signature data to a processor that determines the acceptability of the exposure condition by comparing determined signatures to desired signatures. The system also includes an exposing system that can be controlled to change exposure conditions. The processor selectively controls the exposing system, via the exposer driving system, to adapt such exposure conditions.

Abstract: A system and method are disclosed for providing in-situ monitoring of an oxidized ARC layer disposed over an ARC layer. By monitoring the thickness of the oxidized portion of the ARC layer during semiconductor processing, one or more process control parameters may be adjusted to help achieve a desired oxidized portion thickness.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.