Abstract: A system for regulating (e.g., terminating) a development process is provided. The system includes one or more light sources, each light source directing light to one or more patterns and/or gratings on a wafer. Light reflected from the patterns and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides development related data to a processor that determines the acceptability of the development of the respective portions of the wafer. The collected light may be analyzed by scatterometry and/or reflectometry systems to produce development related data and the development related data may be examined to determine whether a development process end point has been reached, at which time the system can control the development process and terminate development.

Abstract: The invention provides a system and process for depositing films, wherein an acoustic microbalance is used for process monitoring and/or control. The acoustic microbalance is placed in a deposition chamber and may optionally be mounted on a semiconductor substrate, such as a silicon wafer, on which a film is being deposited. Data from the acoustic microbalance is employed to detect a process endpoint, determine an adjustment to process conditions for a subsequent batch, and/or provide feedback control over current process conditions. One aspect of the invention involves the application of a model or database to correct for differences between the extent of deposition on an acoustic microbalance cantilever and the extent of deposition on a substrate being processed. Another aspect of the invention takes a probabilistic approach to employing acoustic microbalance data.

Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: Disclosed are methods of processing a semiconductor structure, involving the steps of depositing a light-degradable surface coupling agent on a semiconductor substrate; depositing a resist over the light-degradable surface coupling agent; irradiating portions of the resist, wherein the light-degradable surface coupling agent under the irradiated portions of the resist at least partially decomposes; and developing the resist.

Abstract: A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.

Abstract: A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Abstract: One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.

Abstract: A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon.

Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.

Abstract: One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.

Abstract: A system and method are disclosed for monitoring characteristics of a substrate. A substrate is supported for movement within a processing environment and an incident light beam is emitted onto a surface of the substrate. The incident beam is provided to a moveable reflector that directs the beam to the substrate. A control system controls movement of the reflector so as to selectively interrogates the substrate with the beam.

Abstract: One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.

Abstract: An exemplary method of forming an attenuating extreme ultraviolet (EUV) phase-shifting mask is described. This method can include providing a multi-layer mirror over an integrated circuit substrate or a mask blank, providing a buffer layer over the multi-layer mirror, providing a dual element material layer over the buffer layer, and selectively growing features on the integrated circuit substrate or mask blank using a photon assisted chemical vapor deposition (CVD) process when depositing the dual element layer.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps.

Abstract: An exemplary method of constructing an alternating phase-shifting mask is described. This method can include providing a vapor in a vapor chamber containing a mask blank, and applying a laser to selected areas of the mask blank to deposit material on the integrated circuit substrate. The material is configured to cause a 180° phase shift at the wavelengths the mask is designed for such as 248 nm, 193 nm or 157 nm.

Abstract: A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.

Abstract: An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

Abstract: One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

Abstract: An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A ground contact is formed from a top insulating layer to a bottom silicon layer. The ground contact extends through the insulating layer, a stop layer, an isolation region and an oxide layer to the bottom silicon layer. The ground contact is fabricated along with the formation of local interconnects.