Patents by Inventor Bhanwar Singh

Bhanwar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6559457
    Abstract: The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: May 6, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6558965
    Abstract: A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: May 6, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Ramkumar Subramanian, Christopher F. Lyons, Marina V. Plat
  • Patent number: 6556303
    Abstract: The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: April 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Michael K. Templeton, Bhanwar Singh, Khoi A. Phan
  • Publication number: 20030068430
    Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.
    Type: Application
    Filed: March 21, 2001
    Publication date: April 10, 2003
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
  • Patent number: 6545753
    Abstract: A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: April 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Michael K. Templeton
  • Patent number: 6545273
    Abstract: The present invention comprises a system for deconvolving tip effects associated with scanning tips in scanning probe microscopes and other scanning systems. The system comprises a scanning system operable to scan a feature or artifact with multiple, different type scanning tips and generate scan data associated therewith and a processor operably coupled to the scanning system. The processor is adapted to determine characteristics associated with the multiple, different type scanning tips using the scan data associated therewith. The present invention also comprises a method of determining scanning probe microscope tip effects. The method comprises the steps of scanning a feature or artifact with a plurality of different type scanning tips, resulting in a plurality of scan data sets associated with the different type scanning tips. The tip effects associated with the different type scanning tips are then deconvolved using the plurality of scan data sets.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: April 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Bharath Rangarajan, Sanjay K. Yedur
  • Patent number: 6541360
    Abstract: A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: April 1, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marina V. Plat, Scott A. Bell, Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh
  • Patent number: 6541184
    Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: April 1, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
  • Publication number: 20030055526
    Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Steven C. Avanzino, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Publication number: 20030052084
    Abstract: A system for monitoring and controlling aperture etching in an alternating aperture phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. The collected light is indicative of properties including the depth, width and/or profile of the openings on the mask. The measuring system provides such depth, width and/or profile related data to a processor that determines the acceptability of the aperture and/or the mask. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor may selectively control the etching devices so as to regulate aperture etching.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Cyrus E. Tabery, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian
  • Patent number: 6535288
    Abstract: The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate comprising an optical indicia and a periodic analysis structure in a periodic manner. The optical indicia is spatially associated with the periodic analysis structure and is utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: March 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Michael K. Templeton, Bhanwar Singh, Khoi A. Phan
  • Patent number: 6534418
    Abstract: An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: March 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marina V. Plat, Scott A. Bell, Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh
  • Patent number: 6528398
    Abstract: An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging layer, removing the exposed portions of the imaging layer, etching the bulk layer at locations where exposed portions of the imaging layer were removed to provide at least one aperture in the bulk layer, and silylating the bulk layer.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Bhanwar Singh, Angela T. Hui
  • Patent number: 6516528
    Abstract: A system and method are disclosed for determining properties of a feature located at a surface of a substrate. A plurality of probe tips are operable to traverse a surface of the substrate and provide measurement data indicative of topographical features scanned thereby. The measurement data obtained from the plurality of probe tips is aggregated and processed to determine feature properties, such as may include line edge roughness and/or linewidth.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: February 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan K. Choo, Bhanwar Singh
  • Patent number: 6513996
    Abstract: One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Michael K. Templeton, Bhanwar Singh
  • Patent number: 6514868
    Abstract: An exemplary method is described which forms a contact hole having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a contact hole is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a contact hole using the hard mask to transfer the second critical dimension to the contact hole.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Angela T. Hui, Bhanwar Singh
  • Patent number: 6514849
    Abstract: An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Angela T. Hui, Bhanwar Singh
  • Patent number: 6514874
    Abstract: A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings. These footings reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Jiahua Yu, Bhanwar Singh, Angela T. Hui
  • Patent number: 6515342
    Abstract: A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Subhash Gupta, Bhanwar Singh, Carmen Morales
  • Patent number: 6514867
    Abstract: An exemplary method is described which forms narrow trench lines having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a trench line is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a trench line using the hard mask to transfer the second critical dimension to the trench line.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Angela T. Hui, Bhanwar Singh