Abstract: A circuit includes a first data line, a first plurality of memory cells coupled with the first data line, and a data transfer circuit coupled with the first data line. The data transfer circuit includes an output logic gate. The data transfer circuit is configured to, in a first operation mode in which the first plurality of memory cells is in a standby mode, set an output node of the output logic gate to be free from electrically coupled with a reference voltage and a supply voltage through the output logic gate. The data transfer circuit is configured to, in a second operation mode in which a memory cell of the first plurality of memory cells is selected to be read, set the output node of the output logic gate to be either electrically coupled with the reference voltage or with the supply voltage through the output logic gate.

Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.

Abstract: The disclosure provides methods for treating a subject having a type I IFN-mediated disease or disorder comprising administration of a fixed does of an anti-interferon alpha receptor antibody. The disclosure also provides methods for suppressing a type I interferon (IFN) gene signature (GS) in a subject. In addition, the disclosure provides methods of prognosing or monitoring disease progression in a subject having a type I IFN-mediated disease or disorder, methods of predicting a dosage regimen, methods of identifying a candidate therapeutic agent, methods of identifying a patient as a candidate for a therapeutic agent, and methods of designating a personalized therapy.

Abstract: The invention provides a composition comprising lactoferrin for use in the prevention, amelioration, or treatment of diarrhea, in particular non-infectious weaning diarrhea of infants or children.

Abstract: A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.

Abstract: A cross-correlation based system for watermarking continuous digital media, includes: a) means for retrieving at least one signature parameter (Sj) determined according to a corresponding previous signature (Sj?1) or a predefined initial signature (S0); the S0 being selectable by a user command to a multiplexor that selects either S0 or Sj during the course of generating a signature; and, b) means for encrypting the present signature according to the at least one signature parameter (Sj) to generate a unique digital signature (Ej).

Abstract: A lever control mechanism of a drain valve of a toilet tank has a lever assembly assembled in the wall of the toilet tank and a lever linked to the revolving shaft of the lever assembly. The lever assembly is connected to a deviator, which is disposed with a drive arm; the drive arm is connected to the revolving shaft. The deviator is disposed with a joint portion and at least a leading hole to limit the lever revolving vertically. One end of the lever is run through the leading hole to rotationally connect to the joint portion; the drive arm is revolved by the driving of the revolving shaft to drive the lever revolved in the fan shaped vertical surface limited formed by the joint portion and the leading hole.

Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Abstract: Methods for preventing or reducing the formation of scale in a wet-process phosphoric acid production process by intermixing a water-soluble functional organic reagent with a phosphoric acid at one or more step of the phosphoric acid production process in an amount sufficient to prevent or reduce at least one species of scale are provided.

Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor.

Abstract: Improved processes for making an N-acyl amino acid salt from a fatty alkyl ester or a polyol ester are disclosed. Each process uses a polyol selected from glycerin or propylene glycol in an amount effective to keep the reaction mixture fluid until conversion to the N-acyl amino acid salt reaches the desired level of completion. In one process, a fatty alkyl ester reacts with an amino acid salt in the presence of glycerin or propylene glycol to produce an N-acyl amino acid salt. In another process, a polyol ester reacts with the amino acid salt in the presence of added glycerin or propylene glycol to produce the N-acyl amino acid salt. We surprisingly found that an effective amount of glycerin or propylene glycol minimizes or eliminates reaction mixture solidification or foaming, reduces color, and minimizes the level of di- and tripeptide by-products. In a related process, water is added when conversion of the amino acid salt to the N-acyl amino acid salt is in the range of 50 to 90 mole %.

Abstract: The present invention combines the strengths of the background-subtraction and edge-detection algorithm for parking detection. Being computationally efficient, the background-subtraction algorithm is used whenever possible. On the other hand, being robust, the edge-detection algorithm is used at calibration points, or when the background-subtraction algorithm cannot reliably determine the parking state.

Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.

Abstract: A compound having the structure set forth in Formula (I) and Formula (II): wherein the substituents Y, Z, A, B, R1, R2, R3, R4 and R5 are as defined herein. Provided herein are inhibitors of poly(ADP-ribose)polymerase activity. Also described herein are pharmaceutical compositions that include at least one compound described herein and the use of a compound or pharmaceutical composition described herein to treat diseases, disorders and conditions associated with a PTEN deficiency that are ameliorated by the inhibition of PARP activity.

Abstract: Provided herein is are methods of treating Chronic Obstructive Pulmonary Disease (COPD) in a patient, comprising administering to the patient an effective amount of benralizumab or an antigen-binding fragment thereof.

Abstract: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.

Abstract: A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.

Abstract: A compound having the structure set forth in Formula (I) and Formula (II): wherein the substituents Y, Z, A, B, R1, R2, R3, R4 and R5 are as defined herein. Provided herein are inhibitors of poly(ADP-ribose)polymerase activity. Also described herein are pharmaceutical compositions that include at least one compound described herein and the use of a compound or pharmaceutical composition described herein to treat diseases, disorders and conditions that are ameliorated by the inhibition of PARP activity.

Abstract: A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.

Abstract: A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.