Abstract: An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

Abstract: An amplifying circuit includes a compensation unit with a feeding forward path to reduce the effect of the common mode noise on the output signals of a differential amplifier.

Abstract: An amplifying circuit includes a differential amplifier for receiving input signals to generate output signals. A current regulator unit and an input enhancement unit allow the input signals to exceed the normal input range of the differential amplifier. The current regulator unit regulates current in the differential amplifier. The input enhancement unit steers current from a first current path to a second current path based on signal levels of the input signals.

Abstract: An open-drain output circuit for a semiconductor device is provided with compensation circuitry for minimizing fluctuations in a regulated gate voltage applied to the gate of an open-drain output transistor. In one embodiment, a compensation voltage is derived from an input signal to the output circuit and applied to one terminal of a capacitor. A second terminal of the capacitor is coupled to the gate of the open-drain output transistor. The compensation circuit comprises at least one pull-up transistor and at least one pull-down transistor coupled to a first terminal of the capacitance. The capacitance couples the compensation voltage to the gate of the output transistor, thereby compensating for capacitive coupling noise induced in constant-voltage gate signal applied to the gate of the output transistor upon assertion of the input signal to the output circuit.

Abstract: An open-drain output circuit for a semiconductor device is provided with a mechanism for compensating for variations in the length of time that the driver circuit presents valid data at an output terminal of a semiconductor device. In one embodiment, the valid data “data eye” for the driver circuit is reduced for the first bit following extended turn-off of the driver circuit as compared with the valid data eye for subsequent bits, a “first bit data eye phenomenon.” To compensate for the first bit data eye phenomenon, circuitry is provided for causing the driver circuit to turn on earlier when the driver circuit has previously been off for relative to when the driver circuit has not been off for. In one embodiment, the compensation circuitry comprises circuitry for assessing the voltage level present on a specified node in the driver circuit, where that voltage level is indicative of the length of time that the driver circuit has been turned off.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching.

Abstract: Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circuitry coupled to the decode logic circuitry that generates a counter value based on the decoded address. Other embodiments of a structure include a compare circuit that determines whether a page count is complete in a memory structure. The compare circuit includes a holding circuitry that includes a number of latches for holding an encoded version of a memory address. The compare circuit also includes a multiplexing circuitry coupled to the holding circuitry.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: A technique is provided for reducing changes in the amount of a bias voltage that is applied to a device in an integrated circuit due to local changes on a bus providing the reference for the bias voltage signal. Local transients on the reference bus may occur due to the inductance of the integrated circuit packaging. To prevent the local transients from affecting the amount of bias applied to a device, the local bias signal is allowed to move common mode with the local reference signal by isolating the local bias signal from the bias source. The technique also provides for disabling the isolation of the local bias signal from the bias source in response to a control signal.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: One aspect of the present invention is directed to a method and apparatus for boosting the voltage supplied to an output pad driver through a bus connected to a voltage regulator, comprising momentarily connecting the bus to a voltage source and temporarily enabling the voltage regulator to source additional current to an output terminal thereof by temporarily increasing the gate voltage applied to an output transistor of the regulator and by at least one of temporarily supplying a boost current to an output terminal of the regulator through a boost transistor. The demand for gate voltage may be periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. A control pulse may also be generated for initializing the enabling step for temporarily sourcing additional current to an output terminal of the voltage regulator.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A technique is provided for reducing changes in the amount of a bias voltage that is applied to a device in an integrated circuit due to local changes on a bus providing the reference for the bias voltage signal. Local transients on the reference bus may occur due to the inductance of the integrated circuit packaging. To prevent the local transients from affecting the amount of bias applied to a device, the local bias signal is allowed to move common mode with the local reference signal by isolating the local bias signal from the bias source. The technique also provides for disabling the isolation of the local bias signal from the bias source in response to a control signal.

Abstract: The present invention is directed to a method and apparatus for providing variable output drive capability to an output driver. One aspect of the present invention is related to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the pre-driver output stages in each output path. Another aspect of the present invention is related to a method of correcting output skews in a subsequent amplification stage. Other aspects of the present invention relate to a portion of a data path, a memory device, and a computer system all having a pre-driver with pre-driver output transistors responsive to signals indicative of the strength of output drive transistors.