Abstract: The present invention is directed to a method and apparatus for providing variable output drive capability to an output driver. One aspect of the present invention is related to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the pre-driver output stages in each output path. Another aspect of the present invention is related to a method of correcting output skews in a subsequent amplification stage. Other aspects of the present invention relate to a portion of a data path, a memory device, and a computer system all having a pre-driver with pre-driver output transistors responsive to signals indicative of the strength of output drive transistors.

Abstract: A technique is provided for reducing changes in the amount of a bias voltage that is applied to a device in an integrated circuit due to local changes on a bus providing the reference for the bias voltage signal. Local transients on the reference bus may occur due to the inductance of the integrated circuit packaging. To prevent the local transients from affecting the amount of bias applied to a device, the local bias signal is allowed to move common mode with the local reference signal by isolating the local bias signal from the bias source. The technique also provides for disabling the isolation of the local bias signal from the bias source in response to a control signal.

Abstract: The present invention relates generally to a method and apparatus for changing the output of a voltage regulator by forcing the voltage regulator into a low power mode. One aspect of the present invention is directed to a method of forcing the voltage regulator into a low power mode by increasing the rate at which a bias current, supplied to a differential amplifier within the voltage regulator, is decreased. The differential amplifier is used to set the output of the voltage regulator. Another aspect of the present invention is directed to an apparatus having a first switch for connecting a control signal for controlling a source of bias current for the amplifier to ground and a second switch connected between a resistive and capacitive load connected to an output transistor and a predetermined voltage other than ground.

Abstract: A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an input/output terminal. The circuit and method selectively isolates the reference voltage from the input/output terminal to which output signals are selectively applied. The isolation occurs responsive to detecting that an output signal is being applied to the input/output terminal so that transitions of the output signal are not coupled through the input receiver to generate noise in the reference voltage. In one embodiment, the isolation is provided by placing an isolation circuit between the input receiver and either the input/output terminal or a source of the reference voltage. In another embodiment, the isolation is provided by selectively biasing the input receiver so that coupling of output signal transitions through the input receiver is substantially reduced.

Abstract: Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circuitry coupled to the decode logic circuitry that generates a counter value based on the decoded address. Other embodiments of a structure include a compare circuit that determines whether a page count is complete in a memory structure. The compare circuit includes a holding circuitry that includes a number of latches for holding an encoded version of a memory address. The compare circuit also includes a multiplexing circuitry coupled to the holding circuitry.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: The drive strength of an output driver is maintained substantially constant regardless of the pattern of data provided to an output bus. The output driver includes a plurality of drive elements coupled to a shared voltage bus and a data-pattern-dependent compensation circuit. To compensate for variations in drive strength induced by data pattern changes which introduce changes in the voltage applied to the driver elements by the shared voltage bus, the compensation circuit selectively couples compensation elements in parallel with the driver elements to change their resistance. Thus, drive strength for each driver element is maintained substantially constant regardless of the data pattern.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: The present invention relates generally to a method and apparatus of producing a control pulse of an extended duration for use in a voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator.

Abstract: One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: A method and apparatus for filtering an output voltage of a charge pump to reduce peak values which cause stress. A charge pump generates a pumped voltage which is filtered by an RC filter, for example a one or two Pi filter. The filter reduces the peak values of pump output voltage while reducing the amount of capacitance (and corresponding die size) required.

Abstract: One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration.

Abstract: An open drain driver circuit generates four switching signals to switch respective sets of current driving transistors on and off. The switching signals have slightly different transition times, and the rate at which the magnitude of each switching signal changes during each transition is controlled throughout each transition to maximize the switching times while slowing the rate of change during certain portions of each transition to prevent excessive changes in the rate at which the current changes. As a result, voltage transients generated in power supply lines coupled to the driver circuit have relatively small peak amplitude.

Abstract: One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration.

Abstract: One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in a output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.