Patents by Inventor Bruce A. Block

Bruce A. Block has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9507086
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 29, 2016
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Publication number: 20160282698
    Abstract: A high index contrast waveguide device is disclosed and described. In one embodiment the waveguide may include a lithium niobate substrate, a waveguide with a higher refractive index than that of the lithium niobate substrate patterned on a surface thereof, and an electrode electrically coupled to the waveguide.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventor: Bruce A. Block
  • Patent number: 9182544
    Abstract: PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Miriam R. Reshotko, Ibrahim Ban, Bruce A. Block, Peter L. Chang
  • Patent number: 9063254
    Abstract: A metal-semiconductor-metal (MSM) device couples light from an optical mode in a waveguide to a surface plasmon polarition (SPP) mode on an electrode surface of the MSM device. Once in an SPP mode, the absorption of light in the semiconductor can take place in a very small area. This may allow for a shrinking of the active detector area and allow for low capacitance, very short transit distance for the electrical carriers and allow for very low voltage devices and/or very high frequency.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventor: Bruce A. Block
  • Patent number: 9036954
    Abstract: Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, four-fold, five-fold, etc.). Embodiments of the invention further enable the electrode length required to create the desired electro-optic effect for the multi-segment optical waveguide to be reduced. In embodiments of the invention, certain electrodes may be “shared” amongst the different segments of the waveguide, thereby reducing the power requirement and capacitance of a device having a waveguide of a given length.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Bruce A. Block, Peter L. Chang
  • Publication number: 20140203175
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 24, 2014
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Publication number: 20140086523
    Abstract: EOP-based photonic devices employing coplanar electrodes and in-plane poled chromophores and methods of their manufacture. In an individual EOP-based photonic device, enhanced performance is achieved through in-plane poled chromophores having opposing polarities, enabling, for example, a push-pull optical modulator with reduced operational voltage and switching power relative to a conventional MZ modulator. For a plurality of EOP-based photonic devices, enhanced manufacturability is achieved through a sacrificial interconnect enabling concurrent in-plane poling of many EOP regions disposed on a substrate.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Bruce A. BLOCK, Mauro J. KOBRINSKY, Miriam R. RESHOTKO, Shawna M. Liff
  • Publication number: 20130336346
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an opto-electronic assembly includes a first semiconductor die including a light source to generate light, and a first mode expander structure comprising a first optical material disposed on a surface of the first semiconductor die, the first optical material being optically transparent at a wavelength of the light, and a second semiconductor die including a second mode expander structure comprising a second optical material disposed on a surface of the second semiconductor die, the second material being optically transparent at the wavelength of the light, wherein the second optical material is evanescently coupled with the first optical material to receive the light from the first optical material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 5, 2012
    Publication date: December 19, 2013
    Inventors: Mauro J. Kobrinsky, Jia-Hung Tseng, Bruce A. Block
  • Publication number: 20130287333
    Abstract: A metal-semiconductor-metal (MSM) device couples light from an optical mode in a waveguide to a surface plasmon polarition (SPP) mode on an electrode surface of the MSM device. Once in an SPP mode, the absorption of light in the semiconductor can take place in a very small area. This may allow for a shrinking of the active detector area and allow for low capacitance, very short transit distance for the electrical carriers and allow for very low voltage devices and/or very high frequency.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 31, 2013
    Inventor: Bruce A. Block
  • Publication number: 20130279845
    Abstract: PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 24, 2013
    Inventors: Mauro J. Kobrinsky, Miriam R. Reshotko, Ibrahim Ban, Bruce A. Block, Peter L. Chang
  • Patent number: 8417070
    Abstract: A metal-semiconductor-metal (MSM) device couples light from an optical mode in a waveguide to a surface plasmon polarition (SPP) mode on an electrode surface of the MSM device. Once in an SPP mode, the absorption of light in the semiconductor can take place in a very small area. This may allow for a shrinking of the active detector area and allow for low capacitance, very short transit distance for the electrical carriers and allow for very low voltage devices and/or very high frequency.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: April 9, 2013
    Assignee: Intel Corporation
    Inventor: Bruce A. Block
  • Patent number: 8290325
    Abstract: Embodiments of the present invention describe a waveguide-based photodetector device and its methods of fabrication. The waveguide photodetector device comprises a substrate having a cladding structure formed thereon. A waveguide element for receiving optical signals is disposed within the cladding structure. A portion of the waveguide element is encapsulated by a photodetector element that detects the optical signal received by the waveguide element and generates an electrical signal based on the optical signal. Encapsulating the waveguide element in the photodetector element improves coupling efficiency and enables a waveguide photodetector device with higher speeds and higher responsivity.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Miriam R. Reshotko, Bruce A. Block
  • Publication number: 20120251029
    Abstract: Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, four-fold, five-fold, etc.). Embodiments of the invention further enable the electrode length required to create the desired electro-optic effect for the multi-segment optical waveguide to be reduced. In embodiments of the invention, certain electrodes may be “shared” amongst the different segments of the waveguide, thereby reducing the power requirement and capacitance of a device having a waveguide of a given length.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: MAURO J. KOBRINSKY, BRUCE A. BLOCK, PETER L. CHANG
  • Patent number: 7960226
    Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List, Ruitao Zhang
  • Publication number: 20110075962
    Abstract: A metal-semiconductor-metal (MSM) device couples light from an optical mode in a waveguide to a surface plasmon polarition (SPP) mode on an electrode surface of the MSM device. Once in an SPP mode, the absorption of light in the semiconductor can take place in a very small area. This may allow for a shrinking of the active detector area and allow for low capacitance, very short transit distance for the electrical carriers and allow for very low voltage devices and/or very high frequency.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventor: Bruce A. Block
  • Patent number: 7893481
    Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Richard Scott List, Bruce A. Block, Ruitao Zhang
  • Publication number: 20100304514
    Abstract: In an embodiment, light from a single mode light source may be deflected into a low index contrast (LIC) waveguide in an opto-electronic integrated circuit (OEIC) (or “opto-electronic chip”) by a 45 degree mirror. The mirror may be formed by polishing an edge of the die at a 45 degree angle and coating the polished edge with a metal layer. Light coupled into the LIC waveguide may then be transferred from the LIC waveguide to a high index contrast (HIC) waveguide by evanescent coupling.
    Type: Application
    Filed: July 13, 2010
    Publication date: December 2, 2010
    Inventors: Bruce A. Block, Paul Davids
  • Patent number: 7843036
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List
  • Publication number: 20100260453
    Abstract: The waveguide in the ring and the bus waveguide in the immediate vicinity of the ring are made wider than the optimal single mode size. The bus waveguide has adiabatic tapers which serve to connect single mode portions in the bus waveguide to the wider portion of the bus waveguide to expand the mode from the narrower waveguide to the wider waveguide. Since the light is now spread out over a larger area in the wider waveguides, the scattering loss from the sidewalls is reduced and the loss is lower. This lower loss gives rise to a higher Q in the ring since the Q of the ring is directly proportional to the round trip loss.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Inventor: Bruce A. Block
  • Patent number: 7801397
    Abstract: In an embodiment, light from a single mode light source may be deflected into a low index contrast (LIC) waveguide in an opto-electronic integrated circuit (OEIC) (or “opto-electronic chip”) by a 45 degree mirror. The mirror may be formed by polishing an edge of the die at a 45 degree angle and coating the polished edge with a metal layer. Light coupled into the LIC waveguide may then be transferred from the LIC waveguide to a high index contrast (HIC) waveguide by evanescent coupling.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Paul Davids