Abstract: In an embodiment of the invention, an optical coupler couples light unidirectionally from integrated circuit package to an integrated circuit die. The package has a large waveguide with a waveguide core that has a low index of refraction. The die has a set of very small waveguide cores that have a high index of refraction relative to the index of refraction of the large waveguide core on the package. The waveguide cores with high index of refraction attract light from the waveguide core with the low index of refraction. No light is coupled back into the large waveguide core. Also, the optical mode of the large waveguide on the package is smaller than a subset of waveguide cores on the die. Thus, light is coupled from the package to the die without the waveguide cores having to be tightly aligned with each other.

Abstract: A microchip may include an optical signal routing system. The optical routing system may include a distribution waveguide coupled to a light source and signaling waveguides interconnecting source and destination locations. A directional coupler may be used to couple and modulate light from the distribution waveguide to a signaling waveguide at a source location. A photodetector may be used to convert light signals from the source location into electrical signals at the destination.

Abstract: Optical waveguide devices having adjustable waveguide cladding wherein the waveguide cladding is adjustable by using an external control or stimulus to change an optical characteristic of the waveguide cladding, e.g., the refractive index of the cladding. Such waveguide devices may be designed to have certain features that are suitable for monolithically integrated opto-electronic devices and systems.

Abstract: In an embodiment of the invention, an optical coupler couples light unidirectionally from integrated circuit package to an integrated circuit die. The package has a large waveguide with a waveguide core that has a low index of refraction. The die has a set of very small waveguide cores that have a high index of refraction relative to the index of refraction of the large waveguide core on the package. The waveguide cores with high index of refraction attract light from the waveguide core with the low index of refraction. No light is coupled back into the large waveguide core. Also, the optical mode of the large waveguide on the package is smaller than a subset of waveguide cores on the die. Thus, light is coupled from the package to the die without the waveguide cores having to be tightly aligned with each other.

Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.

Abstract: In an embodiment, light from a single mode light source may be deflected into a low index contrast (LIC) waveguide in an opto-electronic integrated circuit (OEIC) (or “opto-electronic chip”) by a 45 degree mirror. The mirror may be formed by polishing an edge of the die at a 45 degree angle and coating the polished edge with a metal layer. Light coupled into the LIC waveguide may then be transferred from the LIC waveguide to a high index contrast (HIC) waveguide by evanescent coupling.

Abstract: A microchip may include an optical clocking system. The optical clocking system may include a ring resonator which multiplies the frequency of light pulses from a light source for use as optical clocking signals and distribution waveguides to distribute the optical clocking signals to different regions of the microchip.

Abstract: A microchip may include an optical signal routing system. The optical routing system may include a distribution waveguide coupled to a light source and signaling waveguides interconnecting source and destination locations. A directional coupler may be used to couple and modulate light from the distribution waveguide to a signaling waveguide at a source location. A photodetector may be used to convert light signals from the source location into electrical signals at the destination.

Abstract: A waveguide includes a waveguide core that has a bottom surface and a top surface that defines an angle. The waveguide also includes a cladding layer adjacent to the bottom surface. The cladding layer has a thickness equal to or greater than an evanescent tail of a mode to be transmitted along the wave guide core.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: An integrated waveguide and photodetector which are evanescently coupled, and methods of making such integrated waveguide and photodetector.

Abstract: A microchip includes optical layers with integrated waveguides and modulators. A continuous wave light beam coupled to incoming waveguide(s) is modulated and transmitted off-chip by outgoing waveguides coupled to optical interconnects.

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract: An apparatus having a waveguide with a first tapered surface and a photodetector with a second surface shaped to mate with the first tapered surface.

Abstract: A three dimensional capacitor fabricated as part of a dual damascene process is disclosed. The capacitor structure comprises two barrier metal layers separated by a high k dielectric and is formed in all the via and trench openings. The upper barrier layer and dielectric is selectively removed from those openings which will have ordinary vias and conductors, the other opening remains as capaitor.

Abstract: A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

Abstract: A method of fabricating a decoupling capacitor includes depositing a first barrier metal on a conducting metal. The first barrier metal acts as a first electrode of the decoupling capacitor. A dielectric is deposited on the first barrier metal. A second barrier metal is deposited on the dielectric. The second barrier metal acts as a second electrode of the decoupling capacitor. A photoresist is exposed to ultraviolet light. The photoresist is applied on the second barrier metal. A mask is utilized to define an approximate shape of the decoupling capacitor. A portion of the second barrier metal is etched. A quantity of the photoresist is removed.