Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.

Abstract: Provided herein are compositions for treating a disorder or a disease associated with or characterized by neuro-inflammation, neuro-apoptosis, or neuro-oxidative damage in a subject, pharmaceutical compositions comprising the compositions and pharmaceutically acceptable excipients, and pharmaceutical formulations comprising the compositions. Provided also herein are methods of treating a disorder or a disease associated with or characterized by neuro-inflammation, neuro-apoptosis, or neuro-oxidative damage in a subject, and methods of regulating inflammation, antioxidant enzymes, and apoptosis in a subject having a disorder or a disease associated with or characterized by neuro-inflammation, neuro-apoptosis, or neuro-oxidative damage.

Abstract: A fluorescence lifetime measurement apparatus according to an embodiment of the present invention includes an illumination light generation unit that generates illumination light, a fluorescence photon detection unit that collects fluorescence photons generated by illuminating a sample including fluorescent molecules with the illumination light, a conversion unit that converts the collected fluorescence photons into a first clock signal and converts illumination light that does not pass through the sample into a second clock signal, a first module that analyzes a fluorescence lifetime of the collected fluorescence photons from the conversion unit, a control unit that designates a range of interest (ROI) of the sample from the first module, and a second module that analyzes a fluorescence lifetime of fluorescence photons corresponding to the ROI.

Abstract: A substrate includes a plurality of pixels arranged in a two-dimensional array structure and has a front side and a back side opposite to the front side. An interconnection is arranged on the front side of the substrate. An insulating layer, a color filter, and a micro-lens are arranged on the back side of the substrate. A pixel separation structure is disposed in the substrate. The pixel separation structure includes a conductive layer having a grid structure in a planar view of the image sensor and surrounds each of the plurality of pixels. A back side contact is vertically overlapped with and electrically connected to a grid point portion of the grid structure of the conductive layer of the pixel separation structure.

Abstract: The present invention relates to pressure generation apparatus and method for superconducting power equipment and, more particularly, to pressure generation apparatus and method for superconducting power equipment, wherein a pressure system separately arranged to apply pressure to liquid nitrogen in the superconducting power equipment is disposed inside a pressure vessel.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A substrate includes a plurality of pixels arranged in a two-dimensional array structure and has a front side and a back side opposite to the front side. An interconnection is arranged on the front side of the substrate. An insulating layer, a color filter, and a micro-lens are arranged on the back side of the substrate. A pixel separation structure is disposed in the substrate. The pixel separation structure includes a conductive layer having a grid structure in a planar view of the image sensor and surrounds each of the plurality of pixels. A back side contact is vertically overlapped with and electrically connected to a grid point portion of the grid structure of the conductive layer of the pixel separation structure.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A tissue excising system includes: a tissue ablation device including an ablation unit ablate a body tissue, and an optical signal transmission module; an image generating unit including a light source configured to provide an optical signal to the optical signal transmission module and an optical interferometer configured to receive an optical signal reflected from the body tissue from the optical signal transmission module; and a display unit configured to display an image by receiving an optical image signal from the image generating unit. The optical signal transmission module line-scans the body tissue by penetrating the optical signal from the light source to the body tissue. The optical interferometer generates the optical image signal by applying optical coherence to the optical signal reflected from the body tissue by line-scanning, and the display unit images an inside of the body tissue, using the optical image signal.

Abstract: A substrate includes a plurality of pixels arranged in a two-dimensional array structure and has a front side and a back side opposite to the front side. An interconnection is arranged on the front side of the substrate. An insulating layer, a color filter, and a micro-lens are arranged on the back side of the substrate. A pixel separation structure is disposed in the substrate. The pixel separation structure includes a conductive layer having a grid structure in a planar view of the image sensor and surrounds each of the plurality of pixels. A back side contact is vertically overlapped with and electrically connected to a grid point portion of the grid structure of the conductive layer of the pixel separation structure.

Abstract: A disk brake having a double self-cooling structure to suppress thermal deformation may include a brake disk having a double cooling structure, which is capable of securing cooling performance of the disk while reducing cost and weight of a vehicle compared with the prior art by configuring a self-cooling structure of the disk that can suppress thermal deformation due to excessive frictional heat during braking a vehicle.

Abstract: Disclosed are a superconducting current-limiting element for a current limiter and a method of manufacturing a superconducting current-limiting element for a current limiter, in which the current-limiting element is formed in series by stacking linear superconducting wires, or is formed in parallel by stacking superconducting wires so that one or more superconducting wires are disposed in the same layer, thus facilitating the formation of the current-limiting element in series or in parallel and obviating the use of a winding machine when manufacturing the current-limiting element.

Abstract: A disk brake having a double self-cooling structure to suppress thermal deformation may include a brake disk having a double cooling structure, which is capable of securing cooling performance of the disk while reducing cost and weight of a vehicle compared with the prior art by configuring a self-cooling structure of the disk that can suppress thermal deformation due to excessive frictional heat during braking a vehicle.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract: Disclosed are a superconducting current-limiting element for a current limiter and a method of manufacturing a superconducting current-limiting element for a current limiter, in which the current-limiting element is formed in series by stacking linear superconducting wires, or is formed in parallel by stacking superconducting wires so that one or more superconducting wires are disposed in the same layer, thus facilitating the formation of the current-limiting element in series or in parallel and obviating the use of a winding machine when manufacturing the current-limiting element.