Abstract: A chip scale package has first and second sets of external signal terminals arranged in rows and columns at respective sides of the bottom surface of the package The spacing between the rows of the first set of signal terminals is greater than the spacing between the rows of the second set of signal terminals. The chip scale packages are mounted to and integrated by a printed circuit board having corresponding lands in each of a plurality of chip scale package regions. Thus, the spacing between adjacent rows of a first set of lands is greater than the spacing between adjacent rows of a second set of lands. The rows of the first lands are spaced wider apart so that a plurality of first signal lines can extend contiguously between each adjacent pair of rows of first lands, in each of the chip scale package regions. A method of designing the printed circuit board lays out the lands of the PCB in rows and columns, sets the spacing thereof, and traces out the signal lines.

Abstract: A memory system, which can improve the operation speed of a data bus and is suitable for widening bandwidth by extending the width of the data bus, and memory modules used for the memory system are provided. In the memory system, data buses of a first channel and data buses of a second channel are extended from a memory controller and are arranged on the left and right of a common control and address bus, respectively. Memory modules of a first group are loaded in the data buses of the first channel and memory modules of a second group are loaded in the data buses of the second channel. Also, in the memory system, the memory modules share the common control and address bus positioned in the center. Also, the memory modules are arranged so that some parts of the memory modules overlap each other and that the memory modules of the first group and the memory modules of the second group cross each other.

Abstract: A memory module for use with a computer system board includes at least one memory chip connected to a bus line conductor and a terminating resistor connected to the bus line conductor. The memory module further includes a connector configured to connect the bus line conductor to bus line of the computer system board. A computer system board includes a bus line including first branch configured to connect to a first memory module and a second branch configured to connect to a second memory module. The computer system board further includes a memory controller coupled to the first and second branches of the bus line at a single pin thereof. In other embodiments, a computer system board includes a bus line having first and second branches. A first switch is operative to selectively couple a first plurality of memory modules to a first branch of a bus line of the system board. A second switch is operative to selectively couple a second plurality of memory modules to the second branch of the bus line.

Abstract: Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the memory interface system uses a terminal voltage that is independent of the supply voltages of the memory and the memory controller, the interface system may be unaffected by voltage differences between the memory supply voltage and the memory controller supply voltage.

Abstract: A semiconductor memory device is disclosed that programmably varies an output pin transmitting output data from a comparator during a test mode. Also disclosed is a read method for the test mode. The semiconductor memory device includes a comparator that compares a plurality of output data read from the memory cell array and an output pin determining unit that programmably varies a pin transmitting an output of the comparator during the test mode. Thus, when multiple semiconductor memory devices are installed in a single memory module, the output pins of the semiconductor memory devices are variously determined using the output pin determining unit so that data can be simultaneously read from more than one semiconductor memory device at a time during a test of a memory module, to thereby reduce the module test time.

Abstract: A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to