Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

Abstract: A shift register unit includes a pull-down sustaining sub-circuit and a pull-down sub-circuit. The pull-down sustaining sub-circuit includes: a first transistor having a control electrode configured to input a pull-down sustaining signal, a first electrode connected to a first power signal terminal, and a second electrode connected to a pull-down node; a first capacitor; and a second transistor having a control electrode connected to an input signal terminal. The pull-down sub-circuit includes: a third transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to a pull-up node, and a second electrode connected to the second power signal terminal; a fourth transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to an output sub-circuit, and a second electrode connected to the second power signal terminal.

Abstract: A pixel structure includes: gate lines and data lines disposed crosswise and a plurality of pixel repetition modules distributed in an array. A pixel repetition module includes: a plurality of pixel units arranged in order, wherein each pixel unit includes three sub-pixels arranged in a triangular structure, and the three sub-pixels in each pixel unit and the three sub-pixels in an adjacent pixel unit are arranged inversely with respect to each other; each pixel unit corresponds to two groups of gate lines, wherein each group of gate lines includes two gate lines parallel to each other, a first group of gate lines are located on a first outer side and a second outer side of the pixel units respectively, and a second group of gate lines are both located between the sub-pixels located in a first row and the sub-pixels located in a second row in the pixel units.

Abstract: Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.

Abstract: A method for controlling a charging time of a display panel includes: during t0+k?t in a (k+1)-th blanking time, writing a data voltage to a gate of a driving transistor, and detecting a voltage Vk_(j,i) of a second electrode of the driving transistor; during a t0+(k+r)?t in a (k+1+r)-th blanking time, writing the data voltage to the gate of the driving transistor, and detecting a voltage Vk+i_(j,i) of the second electrode of the driving transistor; determining whether ?Vj,i=Vk+1_ji?Vk_ji is less than or equal to a target voltage difference VT; if ?Vj,i?VT, taking the T=t0+k?t as an expected charging time of a sub-pixel; if ?Vj,i>VT, cyclically performing the charging step described above to obtain ?Vj,i=Vk+p+1_(j,i)?Vk+p_(j,i), and comparing ?Vj,i with the target voltage difference VT, until ?Vj,i?VT, taking t0+(k+p+r?1)?t as the expected charging time of the sub-pixel. p is taken from 1, and increases by 1 for each cycle.

Abstract: A shift register unit, a gate drive circuit, a display device and a driving method are provided. The shift register unit includes a sub-shift register, a second sub-shift register and an output control circuit. The first sub-shift register includes a first output terminal and a first control node, and is configured to output a first clock signal under control of a level of the first control node. The second sub-shift register include a second output terminal and a second control node, and the second output terminal outputs a display output signal in a display phase and a random output signal in a blank phase under control of a level of the second control node. The output control circuit is connected to the first sub-shift register and the second control node, and is configured to control the level of the second control node under control of an output control signal.

Abstract: An OR logic operation circuit and a driving method, a shift register unit, a gate drive circuit, and a display device are provided. The OR logic operation circuit includes: a first inverter, a second inverter, a first control circuit, and a second control circuit. The first inverter is configured to invert a first control signal, which is received, to output a second control signal; the second inverter is configured to invert a third control signal received to output a fourth control signal; the first control circuit is configured to perform first control on a first node and the output terminal to achieve an OR operation and output a first level of an output signal at the output terminal; and the second control circuit is configured to perform second control on the first node and the output terminal to output a second level of the output signal at the output terminal.

Abstract: The present disclosure provides a driving unit, a driving method thereof, a gate driving circuit, and a display substrate. The driving unit includes: a shift register including a pull-up node, a pull-down node and a driving signal output terminal; and a first output circuit including a first control sub-circuit, a second control sub-circuit, an output sub-circuit, and a first signal output terminal; the first control sub-circuit and the output sub-circuit are coupled at a first node, and the first control sub-circuit, the second control sub-circuit and the output sub-circuit are coupled at a second node.

Abstract: The present disclosure provides an organic light emitting diode (OLED) display device and control method thereof. The OLED display device includes: a plurality of subpixels that are arranged in an array having a plurality of rows and a plurality of columns, wherein at least one of the subpixels comprises a control transistor, a light emitting element, and a drive transistor for driving the light emitting element; a plurality of detection lines, wherein at least one of the detection lines is electrically connected with the control transistors of subpixels in a same column, for detecting an electrical property of the drive transistors of subpixels in the same column through respective control transistors; and a plurality of group detection control lines, wherein at least one of the group detection control lines is electrically connected with control transistors of a subpixel group, the subpixel group comprising subpixels in a first row and subpixels in a second row.

Abstract: A shift register unit includes an input module, a first output module, a first pull-down module, a reset module, and a leakage-proof module. The input module is coupled to a pull-up node, a control signal terminal, and an input signal terminal. The first output module is coupled to the pull-up node, a first output terminal, and a second clock signal terminal. The first pull-down module is coupled to the first output terminal, a first signal terminal, and a first clock signal terminal. The reset module is coupled to a reset signal terminal, the pull-up node, and the first output terminal. The leakage-proof module is coupled to a second signal terminal, the first node, and the pull-up node.

Abstract: The present disclosure provides a display panel, a method thereof and a display device. The display panel includes a gate line group, a gate driving circuit, and a sub-pixel unit group. The sub-pixel unit group includes N rows of sub-pixel units, the gate line group includes (N+1) gate lines. The sub-pixel unit includes a light emitting unit, a pixel driving circuit, and a sensing circuit. The gate driving circuit includes output terminals, and is configured to sequentially output gate scanning signals through the output terminals. Each gate line is coupled to one corresponding output terminal. In the sub-pixel unit group, the pixel driving circuit in a sub-pixel unit in an n-th row is coupled to an n-th gate line; and the sensing circuit in the sub-pixel unit in the n-th row is coupled to a (n+1)-th gate line, where 1?n?N, and n is an integer.

Abstract: A circuit includes an input sub-circuit configured to transmit an input signal from an input signal terminal to a feedback node under control of a first clock signal from a first clock signal terminal; a pull-up node control sub-circuit configured to transmit a feedback signal of the feedback node to a pull-up node under control of a first clock signal from the first clock signal terminal; a feedback sub-circuit configured to transmit a first voltage signal from a first voltage signal terminal to the feedback node under control of the pull-up node; an output sub-circuit configured to transmit a second clock signal from a second clock signal terminal to an output signal terminal under control of the pull-up node; and a pull-down sub-circuit configured to transmit a second voltage signal from a second voltage signal terminal to the output signal terminal under control of a pull-down node.

Abstract: The present application discloses a pixel circuit, including a data-input sub-circuit configured to apply a data voltage from the data line to a first node; a reset sub-circuit configured to reset the second node; a driving-control sub-circuit coupled to a first power supply, the first node, and the second node; a power-storage sub-circuit configured to regulate a voltage difference between the first node and the second node; a light-emitting device coupled to the second node and a second power supply; and a sampling sub-circuit coupled to the data line and the second node and being configured to control the data line to connect with the second node for collecting a voltage signal containing information about electrical properties of the driving-control sub-circuit and being used to generating a compensation voltage for compensating any drifts of the electrical properties.

Abstract: The present disclosure discloses a pixel circuit and a method of controlling the same. The pixel circuit includes: a light-emitting control sub-circuit, configured to transmit a data voltage at a data signal terminal to a first node under control of a first control terminal; a driving sub-circuit, configured to transmit a first power supply voltage at a first power supply terminal VDD to a second node N2 under control of a voltage at the first node; a first sensing sub-circuit, configured to maintain a voltage at the second node to be at a fixed level under control of the first control terminal; a second sensing sub-circuit, configured to transmit the voltage at the second node to a first sensing signal terminal under control of a second control terminal, so that the first sensing signal terminal senses a voltage associated with a threshold voltage of the driving sub-circuit.

Abstract: An electronic panel, a display device and a driving method are disclosed. In the electronic panel, each row of subpixel units is divided into a plurality of subpixel unit groups, and each subpixel unit group includes a first subpixel unit and a second subpixel unit. The first subpixel unit includes a first light emitter unit, a first pixel driving circuit for driving the first light emitter unit to emit light, and a first sensing circuit for sensing the first pixel driving circuit; the second subpixel unit includes a second light emitter unit, a second pixel driving circuit for driving the second light emitter unit to emit light, and a second sensing circuit for sensing the second pixel driving circuit.

Abstract: This application discloses a shift register, a gate drive circuit and a display device. The signal of the input signal terminal is provided to the pull-up node by the input circuit under the control of the input signal terminal; and the signal of the second reference signal terminal is provided to the output signal terminal by the output circuit under the control of the clock signal terminal and the signal of the pull-up node. The signal of the first reference signal terminal is provided to the pull-up node by the reset circuit under the control of the input signal terminal and the clock signal terminal. The pull-down control circuit resets the output signal terminal according to the signal of the first reference signal terminal.

Abstract: Embodiments of the present disclosure provide a method for driving a pixel circuit, a pixel circuit, and a display panel. In this method, a zero-voltage signal is provided to a data signal terminal. A first ON signal is provided to a first scan signal terminal, a second ON signal is provided to a second scan signal terminal, and a first level data signal or the zero-voltage signal is provided to the data signal terminal. Next, a decreased data signal, a second level data signal and the zero-voltage signal are provided to the data signal terminal.

Abstract: A thin film transistor structure and a manufacturing method thereof, a circuit structure, a display substrate and a display device are provided. The thin film transistor structure includes: a base plate, and a first thin film transistor and a second thin film transistor stacked on the base plate. The first thin film transistor and the second thin film transistor share a same active layer.