Abstract: A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels.

Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a plurality of clock signal lines and a plurality of testing terminals. As at least two of the plurality of clock signal lines may be connected to a same testing terminal, as compared with the arrangement of the related art in which one clock signal line is connected to one testing terminal, the array substrates provided by the embodiments of the present disclosure only need to have less testing terminals, and correspondingly, the testing device that is connected to the testing terminals of the array substrate provided by the embodiments of the present disclosure may contain less pins. Therefore, the testing device can have a relatively low production cost and a relatively small volume.

Abstract: A pixel driving circuit, array substrate, display device and method for driving the pixel driving circuit are provided, the circuit includes: a control terminal and a first terminal of a driving switch circuit are respectively coupled to a first terminal of a data input switch circuit and an anode of a light-emitting device, and two terminals of a storage capacitor are respectively coupled to the control terminal of the driving switch circuit and the anode of the light-emitting device, two terminals of an intrinsic capacitor are respectively coupled to a cathode and the anode of the light-emitting device, a first terminal and a second terminal of a reset switch circuit are respectively coupled to the anode and the cathode of the light-emitting device, a capacitance of the intrinsic capacitor is greater than or equal to a preset multiple of a capacitance of the storage capacitor.

Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, and a gate driving circuit. The shift register unit includes an input circuit, a next-stage start circuit, a control circuit, a stabilization circuit, and at least one output circuit. The at least one output circuit each can control a voltage of a signal output terminal according to a voltage of a pull-up node, a voltage of a pull-down node, a first voltage signal, a control clock signal from a control clock signal terminal, and a control voltage signal from a control voltage signal terminal. A high level of a second clock signal begins when a high level of a first clock signal ends, and a high level of a third clock signal begins when a high level of the second clock signal ends.

Abstract: A display substrate includes a first base and a plurality of pixel units arranged in rows and in columns. A pixel unit includes a first light-emitting device, a second light-emitting device and a third light-emitting device. A first effective light-emitting area where the first light-emitting device is located and a second effective light-emitting area where the second light-emitting device is located are arranged at intervals along a first direction, a third effective light-emitting area where the third light-emitting device is located is spaced apart from both the first effective light-emitting area and the second effective light-emitting area arranged along a second direction.

Abstract: A scan driving circuit, a driving method, and a display device is provided. The scan driving circuit includes a first scan unit, a first scan line, a first control circuit, and a first switching circuit. The first scan unit includes a first output terminal configured to output a first scan signal. The first control circuit is connected to the first switching circuit, and the first control circuit is configured to control turn-on or turn-off of the first switching circuit under control of the first control signal. The first scan line is connected to the first output terminal through the first switching circuit, so that the first output terminal is electrically connected to the first scan line when the first switching circuit is turned on.

Abstract: A shift register unit, a driving method, a gate driving circuit, and a display device are disclosed. The shift register unit includes: a shift circuit, used to output, to a first output end during a first time period, a power control signal, and output the power control signal to a second output end during a second time period; and a signal integrated circuit, used to output the power control signal to a third output end in response to the power control signal and a first output signal, output the power control signal to the third output end in response to the power control signal and a second output signal, and output, to the third output end at times other than the first and second time period in response to the power control signal, the first output signal and the second output signal, a first pull-down power signal.

Abstract: An array substrate includes a base substrate (1); a driving transistor (2) on the base substrate (1); an insulating layer (3) on the driving transistor (2), the insulating layer (3) comprising a via hole above a first electrode (21) of the driving transistor (2); a conductive portion (4) on the insulating layer (3); and a light emitting device (6) on the conductive portion (4) and electrically connected to the conductive portion (4). The conductive portion (4) may be electrically connected to the first electrode (21) of the driving transistor (2) through the via hole. The light emitting device (6) may be above the via hole, and an orthographic projection of the light emitting device (6) on the base substrate (1) may cover an orthographic projection of the via hole on the base substrate (1).

Abstract: Embodiments of the present disclosure provide a pixel circuit, a display panel, and a display device. The pixel circuit includes: a first transistor; a light emitting unit, a cathode being grounded; a second transistor; a third transistor; a fourth transistor; and a capacitor, a first terminal being coupled to the control electrode of the third transistor, and a second terminal being coupled to the second electrode of the third transistor.

Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, and a gate driving circuit. The shift register unit includes an input circuit, a next-stage start circuit, a control circuit, a stabilization circuit, and at least one output circuit. The at least one output circuit each can control a voltage of a signal output terminal according to a voltage of a pull-up node, a voltage of a pull-down node, a first voltage signal, a control clock signal from a control clock signal terminal, and a control voltage signal from a control voltage signal terminal. A high level of a second clock signal begins when a high level of a first clock signal ends, and a high level of a third clock signal begins when a high level of the second clock signal ends.

Abstract: An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.

Abstract: The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes a compensation selection circuit, a storage circuit, a blanking input circuit, and a shift register circuit. The compensation selection circuit is configured to provide an input signal to a first node. The storage circuit is configured to store and maintain a voltage difference between a blanking control signal terminal and the first node. The blanking input circuit is configured to provide a blanking input signal to a second node. The shift register circuit is configured to provide a compensation driving signal during a blanking period, and provide a scan driving signal during a display period.

Abstract: An organic light-emitting diode array substrate and manufacturing method thereof, and display apparatus are provided. The organic light-emitting diode array substrate includes: a base substrate; a first metal layer disposed on the base substrate; a first insulating layer disposed on a side of the first metal layer far away from the base substrate; a second metal layer disposed on a side of the first insulating layer far away from the base substrate; the first metal layer includes a first power line, and the second metal layer includes a second power line; the second power line is connected in parallel with the first power line through a first via hole which penetrates the first insulating layer.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: A display panel, a display device, and a driving method of the display panel are provided. The display panel includes a plurality of pixel units arranged in an array and data lines and sensing lines connected to the pixel units, and each of the plurality of pixel units includes a plurality of sub-pixels; all sub-pixels in a same column of pixel units are connected to a same data line, each column of pixel units is respectively connected to two of the sensing lines, and any two adjacent columns of pixel units share one of the sensing line.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.

Abstract: The present application discloses a pixel circuit, including a data-input sub-circuit configured to apply a data voltage from the data line to a first node; a reset sub-circuit configured to reset the second node; a driving-control sub-circuit coupled to a first power supply, the first node, and the second node; a power-storage sub-circuit configured to regulate a voltage difference between the first node and the second node; a light-emitting device coupled to the second node and a second power supply; and a sampling sub-circuit coupled to the data line and the second node and being configured to control the data line to connect with the second node for collecting a voltage signal containing information about electrical properties of the driving-control sub-circuit and being used to generating a compensation voltage for compensating any drifts of the electrical properties.

Abstract: Embodiments of the present disclosure provide a shift register circuitry, a gate driving circuit, a display device, and a driving method. The shift register circuitry includes a blanking input circuit, a display input circuit, an output circuit, and a first control circuit. The blanking input circuit provides a blanking input signal to the pull-up control node and supplies a blanking pull-up signal to the pull-up node. The display input circuit provides a display pull-up signal to the pull-up node in response to the display input signal. The output circuit outputs the output signal to the shift signal output terminal and the pixel signal output terminal under the control of the voltage of the pull-up node. The first control circuit couples the shift signal output terminal to the pixel signal output terminal in response to the display input signal.

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.