Abstract: In an embodiment, a system for managing an electronic card of a vehicle, an apparatus therefor, and a method therefor can include a processor configured to recognize a unique identification of a terminal loaded in the vehicle, compare the unique identification of the terminal loaded in the vehicle with a first unique identification stored in a memory to determine whether the terminal loaded in the vehicle is replaced, and if it is determined that the terminal loaded in the vehicle is replaced with a second terminal different from the first terminal, transmit a second unique identification of the second terminal to a server. The server may update the first unique identification to the second unique identification transmitted from the processor and delete a second electronic card previously issued to the second terminal.

Abstract: The electronic toll collection system includes a mobile device of a first user, a vehicle including a memory configured to store first login information of the first user and second login information of a second user and an IC chip configured to perform payment, and a server configured to communicate with the mobile device and the vehicle. The server, upon receiving the first login information of the first user and sharing condition information for the IC chip from the vehicle, the IC chip as a sharable chip, transmits, upon receiving the second login information of the second user and sharing request information from the vehicle, the received sharing request information to the mobile device, and transmits, upon receiving sharing approval information and sharing condition information from the mobile device, the activation command or deactivation command of the IC chip to the vehicle based on the received sharing condition information.

Abstract: Disclosed are a memory device and a manufacturing method thereof. The disclosed memory device may include a first substrate structure including a plurality of sense amplifiers (S/A) and a peripheral circuit unit, a second substrate structure bonded to a first surface side of the first substrate structure and including a first cell block including a plurality of first memory cells and a plurality of first bit lines, and a third substrate structure bonded to a second surface side of the first substrate structure and including a second cell block including a plurality of second memory cells and a plurality of second bit lines, wherein each of the plurality of first bit lines and each of the plurality of second bit lines may be commonly connected to each of the plurality of sense amplifiers (S/A).

Abstract: A semiconductor memory device includes a bit line extending in a first direction on a substrate, an active pattern on the bit line, a word line on a first sidewall of the active pattern and extending in a second direction, a back gate electrode on a second sidewall of the active pattern and extending in the second direction, a gate isolation pattern on the first sidewall of the active pattern and including a low-k pattern extending in the second direction, and a data storage pattern connected to the second surface of the active pattern. The word line is between the active pattern and the gate isolation pattern, and a vertical distance between the bit line and the word line is greater than a vertical distance between the bit line and the low-k pattern.

Abstract: A semiconductor memory device may include includes a bit line and a back gate strap line extending on a substrate, an active pattern on the bit line and the back gate strap line, a word line on a first side wall of the active pattern, a back gate electrode on a second side wall of the active pattern and connected to the back gate strap line, a data storage pattern connected to a face of the active pattern, and a word line contact plug connected to the word line. A first face of the back gate electrode and a first face of the word line may face the bit line and the back gate strap line. The first face of the back gate electrode may be connected to the back gate strap line. A second face of the word line may be connected to the word line contact plug.

Abstract: A server includes a processor configured to, based on receiving a sharing request for a digital coupon, set a plurality of user accounts to share the digital coupon, and based on using at least a portion of the digital coupon, transmit a display command of a guidance message about a result of using the digital coupon to a plurality of user terminals corresponding to the plurality of user accounts.

Abstract: Provided are a device for analyzing a large-area sample based on an image, a device for analyzing a sample based on an image by using a difference in medium characteristic, and a method for measuring and analyzing a sample by using the same. The device for analyzing a large-area sample includes a first sensor array including sensors disposed while being spaced apart from each other in a first direction, a second sensor array including sensors disposed while being spaced apart from each other in the first direction, and spaced apart from the first sensor array in a second direction, and a control unit that obtains image data for a cell included in the sample by using sensing data of the sensor on the sample, in which the sample is interposed between the first sensor array and the second sensor array.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. In one aspect, a memory system is provided to comprise a memory device including a plurality of memory dies, each memory die including a plurality of memory blocks for storing data and different groups of memory blocks form one or more super blocks; and a memory controller in communication with the memory device and configured to count the number of super blocks in an erase state included in each memory die to identify a first memory die having the smallest number of super blocks in the erase state and a second memory die having the largest number of super blocks in the erase state, and move data stored in a first super block included in the first memory die to a second super block included in the second memory die.

Abstract: A battery pack includes a battery module; a processor having a corner formed by two side plates and an opening at the corner, wherein the processor is electrically connected to the battery module and controls charge/discharge of the battery module; and a corner cover which is coupled to the corner and covers the opening.

Abstract: A battery module includes battery cells stacked with each other, a pair of end plates provided at both ends of the battery cells in the stacking direction of the battery cells, and a fastening unit fastened to the pair of end plates along the stacking direction and configured to press the pair of end plates along the stacking direction.

Abstract: The present technology provides a memory system, including a memory device including a plurality of memory blocks that have been allocated to a plurality of zoned namespaces (ZNSs), and a controller configured to, when a ZNS on which a read command that has been received from a host is to be performed is a target for a background operation in which a data migration occurs, store the read command in a delay queue, calculate a delay time for each of the read commands that have been stored in the delay queue for each preset calculation time cycle, and process the read commands by sequentially outputting the read commands from the delay queue after a delay of the calculated delay time.

Abstract: A battery pack includes a plurality of cell module assemblies having at least one battery cell, and a control module electrically connected to the plurality of cell module assemblies to manage the plurality of cell module assemblies as at least two groups.

Abstract: A battery pack includes a battery module having at least one battery cell, a pack case configured to accommodate the battery module, and a connection guide unit provided on at least one side of the pack case and configured to be accessible to electrical members of two or more connection types.

Abstract: A battery pack includes a first battery module having a first corner formed by two side plates; a processing unit having a second corner formed by two side plates, electrically connected to the first battery module and controlling charge/discharge of the battery module; and a first coupling member having one side fastened to the first corner and the other side fastened to the second corner.

Abstract: The battery pack includes a battery module; a processing unit which is electrically connected to the battery module and configured to control charge/discharge of the battery module, wherein at least one of the battery module or the processing unit is configured to allow another battery module or another processing unit to be coupled to two or more sides thereof.

Abstract: Disclosed is a method of adjusting the performance of a wear leveling operation depending on the pattern of a workload according to a command inputted to a storage device, thereby managing a difference in the count of erase operations between storage areas included in a memory not to exceed a limit value and enabling a wear leveling operation to be performed.

Abstract: The present technology includes a controller and an electronic system including the same. The electronic system includes a memory device including a plurality of zones, each zone capable of storing data, a plurality of hosts configured to output access requests for accessing a selected zone, among the plurality of zones, and a controller configured to select one of the plurality of hosts according to order in which the access requests are received, generate and store a key for confirming the selected host, and transmit the key to the selected host, when the access requests to access the selected zone are received from the plurality of hosts, wherein the selected host transmits an operation request including the key to the controller, and the controller executes the operation request when the key is included in the operation request received from the selected host.

Abstract: A method for manufacturing a high-electron-mobility transistor includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a channel layer and a barrier layer on the channel layer; forming a protective layer on the semiconductor substrate at a position corresponding to a gate opening; forming an overlay layer on the semiconductor substrate in an area around the protective layer, and removing the protective layer to form the gate opening; and forming a p-type layer in and at the gate opening and on the overlay layer. Compared with the prior art, the method for manufacturing a high-electron-mobility transistor lowers the technical threshold of manufacture, allows the threshold voltage (Vth) and ON-resistance (Rds(ON)) of each such transistor to be individually controlled at the desired levels, and can improve product yield effectively.

Abstract: A semiconductor field-effect transistor, a power amplifier comprising the same and a manufacturing method thereof are provided herein. The semiconductor field-effect transistor contains an n-type doped layer arranged close to the edge of the two-dimensional electron gas area in a channel layer; said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.