Abstract: A semiconductor field-effect transistor, a power amplifier comprising the same and a manufacturing method thereof are provided herein. The semiconductor field-effect transistor contains an n-type doped layer arranged close to the edge of the two-dimensional electron gas area in a channel layer; said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.

Abstract: Provided are a device for analyzing a large-area sample based on an image, a device for analyzing a sample based on an image by using a difference in medium characteristic, and a method for measuring and analyzing a sample by using the same. The device for analyzing a large-area sample includes a first sensor array including sensors disposed while being spaced apart from each other in a first direction, a second sensor array including sensors disposed while being spaced apart from each other in the first direction, and spaced apart from the first sensor array in a second direction, and a control unit that obtains image data for a cell included in the sample by using sensing data of the sensor on the sample, in which the sample is interposed between the first sensor array and the second sensor array.

Abstract: A memory system includes a memory device including at least one storage region; and a controller coupled to the memory device. The controller separates write data input from an external device from metadata associated with data stored in the memory device. Based on an operation state of the at least one storage region, the controller stores the write data into a buffer storing data to be transferred to the at least one storage region in the memory device. The controller stores the metadata into the buffer regardless of the operation state of the at least one storage region. The controller transfers the write data or the metadata stored in the buffer to the memory device for storing the write data or the metadata in the memory device.

Abstract: Provided are a device for analyzing a large-area sample based on an image, a device for analyzing a sample based on an image by using a difference in medium characteristic, and a method for measuring and analyzing a sample by using the same. The device for analyzing a large-area sample includes a first sensor array including a plurality of sensors which are disposed while being spaced apart from each other in a first direction, a second sensor array including a plurality of sensors, which are disposed while being spaced apart from each other in the first direction, and spaced apart from the first sensor array in a second direction, and a control unit to obtain image data for a cell included in the sample by using sensing data of the sensor on the sample, in which the sample is interposed between the first sensor array and the second sensor array. An active area of one of the sensor in the first sensor array overlaps an active area of one of the sensors in the second sensor array, in the second direction.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. In one aspect, a memory system is provided to comprise a memory device including a plurality of memory dies, each memory die including a plurality of memory blocks for storing data and different groups of memory blocks form one or more super blocks; and a memory controller in communication with the memory device and configured to count the number of super blocks in an erase state included in each memory die to identify a first memory die having the smallest number of super blocks in the erase state and a second memory die having the largest number of super blocks in the erase state, and move data stored in a first super block included in the first memory die to a second super block included in the second memory die.

Abstract: A memory system includes a nonvolatile memory set including a nonvolatile memory; and a memory controller configured to control the nonvolatile memory set. The memory controller may write data to a memory block in a target memory block pool in the nonvolatile memory set during a target time period existing between a time at which an operation mode for the nonvolatile memory set is changed from a second operation mode to a first operation mode and a time at which a command including information indicating that a host expects a requested operation to be performed in the first operation mode is received from the host, prevent execution of a background operation for the nonvolatile memory set, when the operation mode is the first operation mode, and control a background operation for the nonvolatile memory set to be executable, when the operation mode is the second operation mode.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: The present technology includes a controller and an electronic system including the same. The electronic system includes a memory device including a plurality of zones, each zone capable of storing data, a plurality of hosts configured to output access requests for accessing a selected zone, among the plurality of zones, and a controller configured to select one of the plurality of hosts according to order in which the access requests are received, generate and store a key for confirming the selected host, and transmit the key to the selected host, when the access requests to access the selected zone are received from the plurality of hosts, wherein the selected host transmits an operation request including the key to the controller, and the controller executes the operation request when the key is included in the operation request received from the selected host.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: Provided are a device for analyzing a large-area sample based on an image, a device for analyzing a sample based on an image by using a difference in medium characteristic, and a method for measuring and analyzing a sample by using the same. The device for analyzing a large-area sample includes a first sensor array including a plurality of sensors which are disposed while being spaced apart from each other in a first direction, a second sensor array including a plurality of sensors, which are disposed while being spaced apart from each other in the first direction, and spaced apart from the first sensor array in a second direction, and a control unit to obtain image data for a cell included in the sample by using sensing data of the sensor on the sample, in which the sample is interposed between the first sensor array and the second sensor array. An active area of one of the sensor in the first sensor array overlaps an active area of one of the sensors in the second sensor array, in the second direction.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A memory system includes a nonvolatile memory set including a nonvolatile memory; and a memory controller configured to control the nonvolatile memory set. The memory controller may write data to a memory block in a target memory block pool in the nonvolatile memory set during a target time period existing between a time at which an operation mode for the nonvolatile memory set is changed from a second operation mode to a first operation mode and a time at which a command including information indicating that a host expects a requested operation to be performed in the first operation mode is received from the host, prevent execution of a background operation for the nonvolatile memory set, when the operation mode is the first operation mode, and control a background operation for the nonvolatile memory set to be executable, when the operation mode is the second operation mode.