Patents by Inventor Chan Yang

Chan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030069
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN
  • Publication number: 20240021600
    Abstract: Systems and methods for an integrated circuit layout is disclosed. The integrated circuit layout includes a first block including multiple first cells, each of which has a first cell height, and a second block including multiple second cells, each of which has a second cell height. The first block is disposed next to the second block with a spacing that is either equal to zero or less than any of the first or second cell heights.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Po-Hsien Yen, Jia-Hong Gao, Hui-Zhong Zhuang, Jung-Chan Yang
  • Patent number: 11862620
    Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ling Chang, Jung-Chan Yang, Li-Chun Tien, Ting Yu Chen
  • Patent number: 11853679
    Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Sing Li, Jung-Chan Yang, Ting Yu Chen, Ting-Wei Chiang
  • Publication number: 20230411378
    Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.
    Type: Application
    Filed: August 1, 2023
    Publication date: December 21, 2023
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Kuo-Nan YANG
  • Publication number: 20230399509
    Abstract: The present disclosure relates to a polycarbonate resin composition including 8 to 25% by weight of a polycarbonate (A) having a melt index (300° C., 1.2 kg) of 5 to 15 g/10 min; 45 to 77% by weight of a polycarbonate (B) having a melt index (300° C., 1.2 kg) of greater than 15 g/10 min and 25 g/10 min or less; 8 to 25% by weight of a polysiloxane-polycarbonate copolymer (C); 4.5 to 9% by weight of a room-temperature liquid phosphorus-based flame retardant (D); and 1.5 to 5.5% by weight of a phosphazene compound (E), a method of preparing the polycarbonate resin composition, and a molded article including the polycarbonate resin composition.
    Type: Application
    Filed: February 16, 2023
    Publication date: December 14, 2023
    Inventors: Su Kyoung LEE, Woosoo CHOE, Ryul LEE, Minsu KIM, Choongho KIM, Young Wan KIM, Hee Chan YANG
  • Publication number: 20230393039
    Abstract: The present disclosure relates to a tissue diagnosis device including a plate supporter configured to support a plate on which a reaction region is placed and a sample is placed in the reaction region, a patch controller configured to support the patch which contains a labeling substance that specifically labels the target substance, and control a position of the patch relative to the reaction region so that the patch provides the labeling substance to the reaction region, and a target substance detector configured to detect the labeling substance and detect the target substance included in the tissue sample.
    Type: Application
    Filed: August 2, 2023
    Publication date: December 7, 2023
    Inventors: Dong Young Lee, Chan Yang Lim, Kyung Hwan Kim
  • Publication number: 20230385504
    Abstract: A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.
    Type: Application
    Filed: August 23, 2022
    Publication date: November 30, 2023
    Inventors: Johnny Chiahao LI, Jung-Chan YANG, Jian-Sing LI, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN
  • Patent number: 11831062
    Abstract: A mobile terminal and a mobile terminal antenna production method. The mobile terminal uses an insulation film layer on an insulation rear housing as a carrier of a radiating element of an antenna, and the radiating element is located within the entire mobile terminal. A feed and an electric-conductor are disposed on a circuit board, and the electric-conductor is electrically connected to the feed. There is a gap between the radiating element and the electric-conductor, and the electric-conductor indirectly couples the radiating element in a capacitively coupled manner.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 28, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yu Chan Yang, Chien-Ming Lee, Hanyang Wang, Dong Yu, Yi-Hsiang Liao, Xiaoli Yang, Jiaqing You
  • Patent number: 11831154
    Abstract: A voltage balance circuit includes a battery module connected to an external power source, a voltage dividing module, a detection module and a control module. The battery module includes a plurality of batteries connected in series. The voltage dividing module includes a plurality of bleeder resistors. Each bleeder resistor is connected with one battery in parallel. The detection module includes a plurality of thermistors, fixation resistances and micro-controllers. Each thermistor is arranged beside one bleeder resistor. Each thermistor is connected with one fixation resistance in series. Each micro-controller is connected with one thermistor and the one fixation resistance. The control module includes a plurality of switches and an analog front end component. Each switch is connected with the one bleeder resistor in series. Each switch is connected to the analog front end component, and the analog front end component is connected to the one micro-controller.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 28, 2023
    Assignees: Cheng Uel Precision Industry Co., Ltd., Foxlink Automotive Technology(Kunshan) Co., Ltd., Foxlink Automotive Technology Co., Ltd.
    Inventors: Po Shen Chen, Hao Chiang, Jui Chan Yang, Ming Chun Chang, Tsai Fu Lin
  • Publication number: 20230378267
    Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: Jung-Chan YANG, Hui-Zhong ZHUANG, Lee-Chung LU, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20230377976
    Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN
  • Publication number: 20230359803
    Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Cheng-I HUANG, Hui-Zhong ZHUANG, Chi-Yu LU, Stefan RUSU
  • Patent number: 11808677
    Abstract: According to an aspect of the present disclosure, there is provided a polymerase chain reaction (PCR) patch which is provided as a gel type having a net-like structure forming micro-cavities, wherein at least a part of a plurality of reagents used in a PCR are contained in the micro-cavities, and when the patch contacts with an external region, the reagents contained in the micro-cavities move to at least a portion of the external region, and a PCR of a target DNA included in a sample located in the external region is performed.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 7, 2023
    Assignee: NOUL CO., LTD.
    Inventors: Dong Young Lee, Chan Yang Lim, Kyung Hwan Kim
  • Publication number: 20230343775
    Abstract: A method for semiconductor manufacturing is provided. The method includes defining a first cell level group comprising a first set of pattern features corresponding to a predetermined manufacturing process associated with an layout; determining a first number of cell units based on the first cell level group, wherein each of the first number of cell units is compatible with each other; defining a second cell level group comprising the first set of pattern features and a second set of pattern features; and determining a second number of cell units based on the second cell level group, wherein each of the second number of cell units is compatible with each other. The first set of pattern features and the second set of pattern features are arranged in responsive to sequential operations of the predetermined manufacturing process.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: CHUN-CHI TSAI, JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Publication number: 20230335747
    Abstract: A conductive material pre-dispersed slurry for a secondary battery electrode includes: a conductive material; a dispersant for dispersing the conductive material; and a solvent mixed with the conductive material and the dispersant. The dispersant includes a cellulose-based compound and a vinyl-based or acrylic compound, and the cellulose-based compound and the vinyl-based or acrylic compound in the dispersant have a weight ratio of about 25:1 to 1:25.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Inventors: Hyeong Cheol KIM, Chul HUH, Hwi Chan YANG, Joo Cheol LEE, Ju Kyung HAN, Woo Hyun AN
  • Patent number: 11791213
    Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Publication number: 20230326963
    Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, TING-WEI CHIANG, CHENG-I HUANG, KUO-NAN YANG
  • Publication number: 20230317723
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Publication number: 20230299071
    Abstract: An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Yi-Jui CHANG, Jung-Chan YANG