Patents by Inventor Chan Yang

Chan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11636248
    Abstract: An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting Yu Chen, Li-Chun Tien, Fong-Yuan Chang
  • Patent number: 11637069
    Abstract: A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang, Chih-Liang Chen
  • Publication number: 20230124119
    Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Kuo-Nan YANG
  • Patent number: 11624297
    Abstract: A turbine exhaust unit supporting device that supports a turbine exhaust unit is provided. The turbine exhaust unit supporting device installed at a rear side of a turbine casing to support a turbine exhaust unit through which exhaust gas passing through a turbine is discharged, the supporting device includes a casing supporting block unit installed on an outer circumferential surface of the turbine casing, an exhaust unit supporting block unit spaced apart from the casing supporting block unit and installed on an outer circumferential surface of the turbine exhaust unit, and a rotary coupler including a first end rotatably coupled to the casing supporting block unit and a second end rotatably coupled to the exhaust unit supporting block unit.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 11, 2023
    Inventors: Young Do Lee, Young Chan Yang
  • Publication number: 20230068280
    Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Cheng-Yu LIN, Jung-Chan YANG, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Kuo-Nan YANG, Chih-Liang CHEN, Lee-Chung LU
  • Publication number: 20230060387
    Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Patent number: 11581314
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting Yu Chen, Min Cao, Yung-Chin Hou
  • Patent number: 11574110
    Abstract: A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Publication number: 20230022333
    Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.
    Type: Application
    Filed: April 22, 2022
    Publication date: January 26, 2023
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN
  • Publication number: 20230027840
    Abstract: Disclosed is a method of analyzing a programmable logic controller (PLC) logic to detect whether an anomaly that deviates from a standard pattern occurs in a repeated cycle. After modeling and patterning an operation pattern of automation equipment and processes with a graph, an anomaly detecting model capable of detecting whether a pattern is abnormal may be constructed as a graph AutoEncoder model. By detecting the change in the process pattern, it is possible to early detect the anomaly of the equipment and processes.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 26, 2023
    Applicant: UDMTEK CO., LTD.
    Inventors: Gi Nam Wang, Jun Pyo Park, Seung Woo Han, Geun Ho Yu, Min Young Jung, Hee Chan Yang, Seung Jong Jin
  • Patent number: 11556688
    Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Sing Li, Hui-Zhong Zhuang, Jung-Chan Yang, Ting Yu Chen, Ting-Wei Chiang, Tzu-Ying Lin, Li-Chun Tien
  • Publication number: 20230009655
    Abstract: The present disclosure relates to an immunoassay method for performing immunoassay by using a patch that contains antibodies. An immunoassay method according to an aspect of the present disclosure performs diagnosis by detecting a target protein from a sample to be diagnosed by using a patch which includes a mesh structural body forming micro-cavities and is configured to contain a liquid substance in the micro-cavities, and includes placing the sample to be diagnosed in a reaction region, and providing an antibodies that react specifically with a target protein to the reaction region by using a patch that contains the antibodies.
    Type: Application
    Filed: June 16, 2022
    Publication date: January 12, 2023
    Inventors: Dong Young LEE, Chan Yang LIM, Kyung Hwan KIM
  • Patent number: 11552069
    Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Kuo-Nan Yang
  • Patent number: 11542830
    Abstract: A vibration damper capable of damping vibrations occurring from a turbine casing, an exhaust diffuser system including the vibration damper, and a gas turbine including the exhaust diffuser system are provided. The vibration damper installed on an outer casing of a gas turbine to damp vibrations generated in the gas turbine, the vibration damper includes a reinforcing support part including a plurality of reinforcing plates, a first flange coupled to both longitudinal ends of the reinforcing support part and fixed to a protruding support protruding from the outer casing, and a second flange disposed between the plurality of reinforcing plates to connect the plurality of reinforcing plates, wherein each of the plurality of reinforcing plates is erected and installed on an outer circumferential surface of the outer casing.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: January 3, 2023
    Assignee: DOOSAN ENERBILITY CO., LTD.
    Inventor: Young Chan Yang
  • Publication number: 20220382948
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20220382951
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
  • Publication number: 20220379774
    Abstract: A multi-position seat configured to maximize usability thereof through various changes in the positions of a seat back and a seat cushion may include a height assembly configured to move a base frame mounted on a vehicle body, a slide assembly configured to move a seat cushion frame, which is positioned above the base frame and is connected to the base frame via a link mechanism, upwards and downwards by sliding action of the link mechanism in a forward and backward direction, a tilt assembly configured to move a rear end portion of the seat cushion frame upwards and downwards, and a seat back frame hingedly coupled to a rear end portion of the base frame to be reclined.
    Type: Application
    Filed: November 22, 2021
    Publication date: December 1, 2022
    Applicants: Hyundai Motor Company, Kia Corporation, Hyundai Transys, Inc., Daechang Seat Co., LTD-Dongtan
    Inventors: Eun Sue KIM, Seung Sik HAN, Hong Heui LEE, Myung Hoe KIM, Jong Tak LEE, Hae Dong KWAK, Cheol Hwan YOON, Jun Sik HWANG, In Sun BAEK, Sin Chan YANG, Myung Soo LEE, Chan Ki CHO
  • Patent number: 11508661
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Publication number: 20220368007
    Abstract: A mobile terminal and a mobile terminal antenna production method. The mobile terminal uses an insulation film layer on an insulation rear housing as a carrier of a radiating element of an antenna, and the radiating element is located within the entire mobile terminal. A feed and an electric-conductor are disposed on a circuit board, and the electric-conductor is electrically connected to the feed. There is a gap between the radiating element and the electric-conductor, and the electric-conductor indirectly couples the radiating element in a capacitively coupled manner.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yu Chan YANG, Chien-Ming LEE, Hanyang WANG, Dong YU, Yi-Hsiang LIAO, Xiaoli YANG, Jiaqing YOU
  • Publication number: 20220367629
    Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Jung-Chan YANG, Hui-Zhong ZHUANG, Lee-Chung LU, Ting-Wei CHIANG, Li-Chun TIEN