Patents by Inventor Chandra Mohan

Chandra Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10374980
    Abstract: A network where FC and Ethernet storage traffic share the underlying network. The network extends FC SAN storage specific attributes to Ethernet storage devices. The network is preferably formed of FC switches, so each edge switch acts as an FCoE FCF, with internal communications done using FC. IP packets are encapsulated in FC packets for transport. Preferably, either each outward facing switch port can be configured as an Ethernet or FC port, so devices can be connected as desired. FCoE devices connected to the network are in particular virtual LANs (VLANs). The name server database is extended to include VLAN information for the device and the zoning database has automatic FCOE_VLAN zones added to provide a mechanism for enhanced soft and hard zoning. Zoning is performed with the conventional zoning restrictions enhanced by including the factor that any FCoE devices must be in the same VLAN.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 6, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Jesse Willeke, Kiran Sangappa Shirol, Chandra Mohan Konchada
  • Patent number: 10348859
    Abstract: A network where FC and Ethernet storage traffic share the underlying network. The network extends FC SAN storage specific attributes to Ethernet storage devices. The network is preferably formed of FC switches, so each edge switch acts as an FCoE FCF, with internal communications done using FC. IP packets are encapsulated in FC packets for transport. Preferably, either each outward facing switch port can be configured as an Ethernet or FC port, so devices can be connected as desired. FCoE devices connected to the network are in particular virtual LANs (VLANs). The name server database is extended to include VLAN information for the device and the zoning database has automatic FCOE_VLAN zones added to provide a mechanism for enhanced soft and hard zoning. Zoning is performed with the conventional zoning restrictions enhanced by including the factor that any FCoE devices must be in the same VLAN.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 9, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Kiran Sangappa Shirol, Chandra Mohan Konchada
  • Patent number: 10333866
    Abstract: A network where FC and Ethernet storage traffic share the underlying network. The network extends FC SAN storage specific attributes to Ethernet storage devices. The network is preferably formed of FC switches, so each edge switch acts as an FCoE FCF, with internal communications done using FC. IP packets are encapsulated in FC packets for transport. Preferably, either each outward facing switch port can be configured as an Ethernet or FC port, so devices can be connected as desired. FCoE devices connected to the network are in particular virtual LANs (VLANs). The name server database is extended to include VLAN information for the device and the zoning database has automatic FCOE_VLAN zones added to provide a mechanism for enhanced soft and hard zoning. Zoning is performed with the conventional zoning restrictions enhanced by including the factor that any FCoE devices must be in the same VLAN.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 25, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Chandra Mohan Konchada, Kiran Sangappa Shirol, Jesse Willeke
  • Publication number: 20190125715
    Abstract: Triterpenoid drugs such as CDDO-Me can be used as to treat autoimmune diseases such as graft versus host disease, lupus, and lupus nephritis. Triterpenoid drugs can also be used to prevent the effects of an autoimmune disease.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 2, 2019
    Inventors: Chandra Mohan, Tianfu Wu, Michael Andreeff
  • Patent number: 10164873
    Abstract: Systems and methods utilize an all-or-none switchover to prevent split-brain problems in a Multi-Chassis Link Aggregation Group (MC-LAG) network. A standby node in the MC-LAG network can perform the steps of remaining in a standby state responsive to a loss of adjacency with an active node, wherein, in the standby state, all standby links between the standby node and a common endpoint are non-distributing; monitoring frames transmitted by the common endpoint to the standby node over the standby links; and determining based on the monitoring frames whether all active links between the active node and the common endpoint have failed and entering an active state with all the standby links distributing based thereon.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Ciena Corporation
    Inventors: Ankit Sood, Hossein Baheri, Leela Sankar Gudimetla, Vijay Mohan Chandra Mohan, Wei-Chiuan Chen
  • Publication number: 20180351855
    Abstract: Systems and methods utilize an all-or-none switchover to prevent split-brain problems in a Multi-Chassis Link Aggregation Group (MC-LAG) network. A standby node in the MC-LAG network can perform the steps of remaining in a standby state responsive to a loss of adjacency with an active node, wherein, in the standby state, all standby links between the standby node and a common endpoint are non-distributing; monitoring frames transmitted by the common endpoint to the standby node over the standby links; and determining based on the monitoring frames whether all active links between the active node and the common endpoint have failed and entering an active state with all the standby links distributing based thereon.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 6, 2018
    Inventors: Ankit SOOD, Hossein BAHERI, Leela Sankar GUDIMETLA, Vijay Mohan CHANDRA MOHAN, Wei-Chiuan CHEN
  • Publication number: 20180351010
    Abstract: A process of depositing zirconium oxide (ZrO2) layers possessing dual properties of anti-reflection and passivation of silicon surfaces, including passivation of n-type and p-type silicon substrates. To grow a ZrO2 anti-reflection passivation layer, a precursor layer of zirconium oxide is spun on a silicon surface then dried, pyrolyzed and fired at suitable contact firing conditions, avoiding additional deposition. Thermal annealing in a hydrogen environment improves passivation quality of ZrO2 layer to a level 3-4 times higher than that of fired films alone. ZrO2 dielectric passivation layers exhibit improved passivation quality after illumination due to photo-enhanced passivation and higher passivation quality at higher thermal budget suitable for screen printed metal contact firing, unlike standard PECVD deposited passivation layers. The method is adaptable for fabrication of silicon solar cells and other structures utilizing passivated layers.
    Type: Application
    Filed: November 22, 2016
    Publication date: December 6, 2018
    Applicant: Council of Scientific & Industrial Research
    Inventors: Prathap Pathi, Rani Kalpana, Sanjay Kumar Srivastava, Chandra Mohan Singh Rauthan, Parakram Kumar Singh
  • Patent number: 9893984
    Abstract: Embodiments of the present invention provide path MTU discovery of a network path, such as an IPv4 network. According to various embodiments of the invention, a node receives a packet at a node along the network path between a source node and a destination node, compares a MTU size of a next hop along the network path with the size of the packet, responsive to the MTU size of the next hop along the network path being less than the size of the packet and responsive to the packet supporting path MTU discovery, the node truncates the packet to the MTU size of the next hop, stores the MTU size in the portion of the packet reserved for PMTU size, and forwards the packet.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: February 13, 2018
    Assignee: DELL PRODUCTS LP
    Inventors: Chandra Mohan Sundar, Pugalendran Rajendran
  • Publication number: 20180005609
    Abstract: Disclosed herein is a display controller and display controller techniques to self-refresh a non-self-refresh display. The display controller can be configured to determine when display data is static. During periods where display data is static, the display controller can cache display data output in device memory and “refresh” the display data using the cached display data output. A display controller can receive a number of display data elements to be overlaid. The display controller can blend the display data elements into blended display data and can send the blended display data to a display. The display controller can determine whether the display data elements are static. The display controller can cache the blended display data based on determining that the display data elements are static and can send the cached blended display data to the display every refresh while the display data elements are no longer static.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: INTEL CORPORATION
    Inventor: Chandra Mohan Konduru
  • Publication number: 20170179000
    Abstract: Thermoelectric coolers having solderless electrical interconnects, and semiconductor packages incorporating such thermoelectric coolers, are described. In an example, a thermoelectric cooler includes a solderless electrode electrically connecting a P-type semiconductor column to an N-type semiconductor column, and the solderless electrode is in direct contact with diffusion barrier layers separating the solderless electrode from the P-type and N-type semiconductor material layers of the semiconductor columns. Methods of manufacturing thermoelectric coolers having solderless electrical interconnects are also described.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Chandra Mohan JHA, Kelly Porter LOFGREEN
  • Patent number: 9654122
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: May 16, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan
  • Publication number: 20160373123
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 22, 2016
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan
  • Patent number: 9450593
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan
  • Publication number: 20160234101
    Abstract: Embodiments of the present invention provide path MTU discovery of a network path, such as an IPv4 network. According to various embodiments of the invention, a node receives a packet at a node along the network path between a source node and a destination node, compares a MTU size of a next hop along the network path with the size of the packet, responsive to the MTU size of the next hop along the network path being less than the size of the packet and responsive to the packet supporting path MTU discovery, the node truncates the packet to the MTU size of the next hop, stores the MTU size in the portion of the packet reserved for PMTU size, and forwards the packet.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Applicant: DELL PRODUCTS L.P.
    Inventors: Chandra Mohan Sundar, Pugalendran Rajendran
  • Patent number: 9356879
    Abstract: Embodiments of the present invention provide path MTU discovery of a network path, such as an IPv4 network. According to various embodiments of the invention, a node receives a packet at a node along the network path between a source node and a destination node, compares a MTU size of a next hop along the network path with the size of the packet, responsive to the MTU size of the next hop along the network path being less than the size of the packet, a DF flag being set to not allow fragmentation, a RC flag being set to identify that a portion of the packet is reserved for PMTU size, and a PMTU bit being set to positive, truncates the packet to the MTU size of the next hop, stores the MTU size in the portion of the packet reserved for PMTU size, and forwards the packet.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 31, 2016
    Assignee: DELL PRODUCTS L.P.
    Inventors: Chandra Mohan Sundar, Pugalendran Rajendran
  • Publication number: 20160117924
    Abstract: A security alert system for providing real time security alerts comprises a device storing and sending data. A tracking platform server receives data from the device and sends data to a messaging service. A tracking server is provided for receiving data from the messaging service. The tracking server has business logic for processing data received from the tracking platform server. The tracking server monitors data and raise alert if the required condition is satisfied. A client side component is included for interacting with a customer through a browser. The client side component polls to the tracking server to get a new alert or status of the existing alert. The client side has a configuration part wherein the user can configure an alert condition.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 28, 2016
    Inventors: Vishwastam SHUKLA, SOURAV AGARWAL, CHANDRA MOHAN MEENA, KANIKA KAPOOR
  • Publication number: 20160087642
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 24, 2016
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan
  • Patent number: 9260781
    Abstract: A plasma based deposition process to deposit thin film on the inner surfaces of the shaped objects such as plastic or metallic object like bottles, hollow tubes etc. at room temperature has been developed. In present invention uniform hydrogenated amorphous carbon (also called Diamond-Like Carbon, DLC) films on inner surfaces of plastic bottles is successfully deposited. Applications of such product include entire food and drug industries. There is a huge demand of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN)) bottles, meant for the storage of potable water, carbonated soft drinks, wines, medicines etc. However, the higher cost prohibits their wide, spread use. The cheaper alternative is to use plastic bottles inside coated with chemically inert material such as Diamond-Like Carbon (DLC) will be commercially viable. Inventor process can be scaled up for mass production.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: February 16, 2016
    Assignee: Council of Scientific and Industrial Research
    Inventors: Sushil Kumar, Prakash Narain Dixit, Chandra Mohan Singh Rauthan
  • Patent number: 9231606
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 5, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan
  • Patent number: 9225349
    Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: December 29, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tom Taoufik Bourdi, Thomas Obkircher, Bipul Agarwal, Chandra Mohan