Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

Abstract: Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader.

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

Abstract: The present invention provides a high voltage direct current (HVDC) transmission system (300, 600) comprising: a first station (102) comprising series-connected first and second HVDC converters (110, 130); a second station (104) comprising series-connected third and fourth HVDC converters (150, 170), wherein a neutral node (164) coupling the third HVDC converter (150) to the fourth HVDC converter (170) is coupled to earth; a first transmission line (200) connecting a positive node (114) of the first HVDC converter (110) to a corresponding positive node (154) of the third HVDC converter (150), wherein a first pole (240) of the system (300, 600) comprises the first HVDC converter (110), the third HVDC converter (150) and the first transmission line (200); a second transmission line (210) connecting a negative node (138) of the second HVDC converter (130) to a corresponding negative node (178) of the fourth HVDC converter (170), wherein a second pole (250) of the system (300, 600) comprises the second HVDC conve

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

Abstract: Disclosed are a system, method and devices for simultaneous MACsec key agreement (MKA) negotiation between the devices. The present application controls a basic TLV message exchange between supplicant and authenticator in case of race condition to establish the secure association key (SAK) channel. The present application by controlling a basic TLV message exchange enables to establish a secure channel in race condition and achieves a high reliability of the product as this makes product launch MACsec services quickly and available for the service. Accordingly, when both sides (two supplicants) exchange hello with basic TLV at the same time, triggering the race condition, drops first message from the authenticator at supplicant and update the peer MN and the supplicant will not send reply. The authenticator when send next message (basic+potential peer TLV) with peer MN incremented by 1, the supplicant will respond with incremental message with live peer TLV.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a lateral heat spreader (LHS) over a package substrate, and a first die over the LHS and package substrate. The first die has a first region and a second region, where the first and second regions are on a bottom surface of the first die. The semiconductor package includes a plurality of second dies over the first die, and an integrated heat spreader (IHS) over the second dies, first die, LHS, and package substrate. The IHS includes a lid and legs. The LHS thermally couples the first region of the first die to the legs of the IHS, and laterally extends from below the first region of the first die to below the legs of the IHS. The LHS may be comprised of graphene sheets, heat pipes, or vapor chambers and coupled to a thermal conductive material and a sealant.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Disclosed are a system, method and devices for simultaneous MACsec key agreement (MKA) negotiation between the devices. The present application controls a basic TLV message exchange between supplicant and authenticator in case of race condition to establish the secure association key (SAK) channel. The present application by controlling a basic TLV message exchange enables to establish a secure channel in race condition and achieves a high reliability of the product as this makes product launch MACsec services quickly and available for the service. Accordingly, when both sides (two supplicants) exchange hello with basic TLV at the same time, triggering the race condition, drops first message from the authenticator at supplicant and update the peer MN and the supplicant will not send reply. The authenticator when send next message (basic+potential peer TLV) with peer MN incremented by 1, the supplicant will respond with incremental message with live peer TLV.

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

Abstract: Methods and systems are provided for predictive maintenance of a vehicle component. One method involves mapping a current instance of a component of a vehicle to one of plurality of degradation groups of prior lifecycles for other instances of the component based on a relationship between performance measurement data for the current instance and historical performance measurement data associated with that respective degradation group, obtaining contextual data associated with operation of the vehicle, and determining a maintenance recommendation for the current instance of the component based on the contextual data using a predictive maintenance model associated with the mapped degradation group.

Abstract: This application relates to methods and apparatus for handling a fault associated with a voltage source converter (VSC) for exchanging electrical power between an AC system (101, 102) and a DC system (106-1, 106-2). The VSC (104) is connected to the AC system via an interface apparatus, comprising a transformer (107) with a set of primary windings (202) for coupling to a plurality of AC phases (A, B, C) of the AC system. In embodiments of the disclosure the set of primary windings having a neutral point (N) and the interface apparatus includes a fault module (301) having an energy storage element (302) connected in parallel with a resistive element (303) between the neutral point of the set of primary windings and a reference voltage, such as ground.

Abstract: A process of depositing zirconium oxide (ZrO2) layers possessing dual properties of anti-reflection and passivation of silicon surfaces, including passivation of n-type and p-type silicon substrates. To grow a ZrO2 anti-reflection passivation layer, a precursor layer of zirconium oxide is spun on a silicon surface then dried, pyrolyzed and fired at suitable contact firing conditions, avoiding additional deposition. Thermal annealing in a hydrogen environment improves passivation quality of ZrO2 layer to a level 3-4 times higher than that of fired films alone. ZrO2 dielectric passivation layers exhibit improved passivation quality after illumination due to photo-enhanced passivation and higher passivation quality at higher thermal budget suitable for screen printed metal contact firing, unlike standard PECVD deposited passivation layers. The method is adaptable for fabrication of silicon solar cells and other structures utilizing passivated layers.

Abstract: An electronic subassembly includes an enclosure, a circuit board, a plurality of electronic components, and a plurality of flexible elastic thermal elements. Each flexible elastic thermal bridge is disposed in the gap between a different one of the electronic components and a first wall of the enclosure. Each flexible elastic thermal bridge includes a first thermally conductive metallic structure, a second thermally conductive metal structure, and an elastically deflectable thermal element. The first thermally conductive metallic structure contacts the first wall. The second thermally conductive metallic structure contacts the top surface of the electronic component and is spaced apart from the first thermally conductive metallic structure to define a void. The elastically deflectable thermal element is disposed in the void and directly contacts both the first thermally conductive metallic structure and the second thermally conductive metallic structure.

Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.

Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.