Patents by Inventor Chandra Mohan

Chandra Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230385469
    Abstract: The present solution, approach or method, including an end-to-end automated data pipeline for data ingestion, storage, analysis, deployment, and a machine learning model maintenance. The present solution, approach or method, which computes a baseline using machine learning methods, may help in the following ways. Accurate real time estimation may help evaluate the deviation in the actual energy consumption, effectively identifying underlying root causes for an increase in actual consumption, as compared to the estimated energy. Triangulating the time of day and place of high energy consumption results in quicker resolution. Accurately quantifying energy savings may be helpful. Forecasting energy consumption in the future, may enable planning for future energy needs. Energy saving calculations may be done by comparing actual consumption versus baseline predicted consumption based for a specific baseline period.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Ananda Vel Murugan Chandra Mohan, Banuprakash Balakrishna, Chhavi Chawla, Deepika Sandeep, Rohil Pal, Surjayan Ghosh, Swaroop Reddy Konala
  • Publication number: 20230343738
    Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.
    Type: Application
    Filed: July 3, 2023
    Publication date: October 26, 2023
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Sergio Antonio Chan Arguedas, Jimin Yao, Chandra Mohan Jha
  • Patent number: 11780609
    Abstract: Methods and systems are provided for predictive maintenance of a vehicle component. One method involves mapping a current instance of a component of a vehicle to one of plurality of degradation groups of prior lifecycles for other instances of the component based on a relationship between performance measurement data for the current instance and historical performance measurement data associated with that respective degradation group, obtaining contextual data associated with operation of the vehicle, and determining a maintenance recommendation for the current instance of the component based on the contextual data using a predictive maintenance model associated with the mapped degradation group.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: October 10, 2023
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Megan L. Hawley, Timothy Griffith, Cavene Robinson, Ananda Vel Murugan Chandra Mohan, Dinkar Mylaraswamy
  • Patent number: 11777401
    Abstract: A converter including a first terminal and a second terminal, the first terminal configured for connection to a first network, the second terminal configured for connection to a second network; at least one switching module arranged to interconnect the first terminal and the second terminal, the switching module including at least one module switching element and at least one energy storage device, the module switching element and the energy storage device arranged to be combinable to selectively provide a voltage source, the switching module switchable to control a transfer of power between the first and second networks; the switching module including a discharge circuit, the discharge circuit including a discharge switching element and a discharge resistor, the discharge switching element switchable to switch the corresponding discharge resistor into and out of the corresponding switching module; and a controller configured to selectively control the switching of the discharge switching element.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 3, 2023
    Assignee: General Electric Technology GmbH
    Inventors: Chandra Mohan Sonnathi, Radnya Anant Mukhedkar, Rajaseker Reddy Ginnareddy
  • Publication number: 20230308470
    Abstract: In one embodiment, a method includes receiving, by a network component, application performance data. The application performance data is associated with one or more applications. The method also includes determining to transform, by the network component, the application performance data into application security data, generating, by the network component, a baseline for the application security data, and detecting, by the network component, an anomaly in the baseline. The method further includes determining, by the network component, a potential security threat based on the anomaly.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Ashutosh Kulshreshtha, Walter T. Hulick, JR., Chandra Mohan Babu Nadiminti
  • Patent number: 11770005
    Abstract: This application relates to methods and apparatus for handling a fault associated with a voltage source converter (VSC) for exchanging electrical power between an AC system (101, 102) and a DC system (106-1, 106-2). The VSC (104) is connected to the AC system via an interface apparatus, comprising a transformer (107) with a set of primary windings (202) for coupling to a plurality of AC phases (A, B, C) of the AC system. In embodiments of the disclosure the set of primary windings having a neutral point (N) and the interface apparatus includes a fault module (301) having an energy storage element (302) connected in parallel with a resistive element (303) between the neutral point of the set of primary windings and a reference voltage, such as ground.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 26, 2023
    Assignee: General Electric Technology GmbH
    Inventors: Radnya Anant Mukhedkar, Chandra Mohan Sonnathi
  • Publication number: 20230288410
    Abstract: Provided herein are vertical flow assay devices for detecting presence or an amount of cytokines in a sample. Also provided herein are immunoassay methods for detecting presence or an amount of cytokines in a sample, using the vertical flow assay devices.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 14, 2023
    Inventors: Chandra Mohan, Rongwei Lei
  • Patent number: 11756856
    Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath Mahajan, Chandra Mohan Jha, Kelly Lofgreen, Weihua Tang
  • Patent number: 11756860
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
  • Patent number: 11735552
    Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Sergio Antonio Chan Arguedas, Jimin Yao, Chandra Mohan Jha
  • Publication number: 20230252162
    Abstract: A computing system for identifying and scoring problems associated with call stacks. The computing system identifies call stacks associated with an application and determines a problem occurs in the application. The computer system compares a call stack of a first set of applications with a call stack of a second set of applications, wherein the call stack of the first set of applications includes the problem and the call stack of the second set of applications does not include the problem. The computer system generates a score indicating a likelihood that a particular call stack caused the problem based on whether the particular call stack is included in the call stack of the first set of applications, the call stack of the second set of applications, or both. The computing system generates a notification comprising the score indicating the likelihood that the particular call stack caused the problem.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 10, 2023
    Inventors: Ashutosh Kulshreshtha, Walter T. Hulick, JR., Chandra Mohan Babu Nadiminti
  • Patent number: 11705417
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Chandra Mohan Jha, Prasad Ramanathan, Xavier F. Brun, Jimmin Yao, Mark Allen
  • Patent number: 11694942
    Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Publication number: 20230197030
    Abstract: One embodiment provides a graphics processor device that includes circuitry configured to detect a connection of a second display device to a display subsystem of the graphics processor while a first display device of the graphics subsystem is active, write pre-determined pixel data to a reserved portion of memory associated with the display subsystem, configure timings for the second display device while resources allocated to the first display device remain available to the first display device, display the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output the framebuffer data to the second display device, and transition the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventor: Chandra Mohan Konduru
  • Patent number: 11670561
    Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chandra Mohan Jha, Je-Young Chang, Chia-Pin Chiu, Liwei Wang
  • Publication number: 20230169448
    Abstract: Examples provide on-time delivery prediction generation using a machine learning element for orders obtained from an order management component. The obtained order is analyzed to identify a plurality of order attributes. An initial value for each order attribute in the plurality of order attributes is calculated based on sensor data and telemetry data. An initial order-score for the obtained order is determined based on the initial values for each order attribute in the plurality of order attributes. An alternative order-score for the order is calculated after identifying an order attribute variable for the order and calculating updated values for each order attributes in the plurality of order attributes. After outputting the initial order-score and the alternative order-score for the order, with an indication of the order attribute variable associated with the alternative order-score, feedback for the order is received.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Inventors: Srinivasan Venkatesan, Sandeep Nayak, Subhash Kumar Dhaka, Shantanu Rai, Balasubrahmanyam Chaturvedula, Chandra Mohan Meena
  • Patent number: 11664293
    Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath V. Mahajan, Chandra Mohan Jha
  • Patent number: 11658095
    Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
  • Publication number: 20230140685
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Shrenik KOTHARI, Chandra Mohan JHA, Weihua TANG, Robert SANKMAN, Xavier BRUN, Pooya TADAYON
  • Publication number: 20230109396
    Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.
    Type: Application
    Filed: October 1, 2022
    Publication date: April 6, 2023
    Inventors: Anjali Singhai JAIN, Nupur JAIN, Elazar COHEN, John Andrew FINGERHUT, Neha SINGH, Vinoth Kumar CHANDRA MOHAN, Alana SWEAT, Arunkumar BALAKRISHNAN