Abstract: In one embodiment, a method includes receiving, by a network component, application performance data. The application performance data is associated with one or more applications. The method also includes determining to transform, by the network component, the application performance data into application security data, generating, by the network component, a baseline for the application security data, and detecting, by the network component, an anomaly in the baseline. The method further includes determining, by the network component, a potential security threat based on the anomaly.

Abstract: This application relates to methods and apparatus for handling a fault associated with a voltage source converter (VSC) for exchanging electrical power between an AC system (101, 102) and a DC system (106-1, 106-2). The VSC (104) is connected to the AC system via an interface apparatus, comprising a transformer (107) with a set of primary windings (202) for coupling to a plurality of AC phases (A, B, C) of the AC system. In embodiments of the disclosure the set of primary windings having a neutral point (N) and the interface apparatus includes a fault module (301) having an energy storage element (302) connected in parallel with a resistive element (303) between the neutral point of the set of primary windings and a reference voltage, such as ground.

Abstract: Provided herein are vertical flow assay devices for detecting presence or an amount of cytokines in a sample. Also provided herein are immunoassay methods for detecting presence or an amount of cytokines in a sample, using the vertical flow assay devices.

Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Abstract: A computing system for identifying and scoring problems associated with call stacks. The computing system identifies call stacks associated with an application and determines a problem occurs in the application. The computer system compares a call stack of a first set of applications with a call stack of a second set of applications, wherein the call stack of the first set of applications includes the problem and the call stack of the second set of applications does not include the problem. The computer system generates a score indicating a likelihood that a particular call stack caused the problem based on whether the particular call stack is included in the call stack of the first set of applications, the call stack of the second set of applications, or both. The computing system generates a notification comprising the score indicating the likelihood that the particular call stack caused the problem.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

Abstract: One embodiment provides a graphics processor device that includes circuitry configured to detect a connection of a second display device to a display subsystem of the graphics processor while a first display device of the graphics subsystem is active, write pre-determined pixel data to a reserved portion of memory associated with the display subsystem, configure timings for the second display device while resources allocated to the first display device remain available to the first display device, display the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output the framebuffer data to the second display device, and transition the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

Abstract: Examples provide on-time delivery prediction generation using a machine learning element for orders obtained from an order management component. The obtained order is analyzed to identify a plurality of order attributes. An initial value for each order attribute in the plurality of order attributes is calculated based on sensor data and telemetry data. An initial order-score for the obtained order is determined based on the initial values for each order attribute in the plurality of order attributes. An alternative order-score for the order is calculated after identifying an order attribute variable for the order and calculating updated values for each order attributes in the plurality of order attributes. After outputting the initial order-score and the alternative order-score for the order, with an indication of the order attribute variable associated with the alternative order-score, feedback for the order is received.

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.

Abstract: A method and a system of deploying an ignition interlock device (IID). The method comprises receiving a time series of breath alcohol content (BrAC) measurements that are unitarily sourced from a pre-identified user, each BrAC measurement of the time series including an alveolar breath component and an interferent breath component; estimating a dissipation rate of alcohol attributable to the pre-identified user in accordance with the time series of BrAC measurements; determining, responsive to estimating the dissipation rate of alcohol, at least a subset of the BrAC measurements as being based on the alveolar breath component but not the interferent breath component; and performing one of triggering and not triggering the IID into a lockout state based on the at least a subset of the BrAC measurements.

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

Abstract: Embodiments of the disclosure include an electrical assembly. The electrical assembly can include a converter including a DC side and an AC side, the DC side configured for connection to a DC network, the AC side configured for connection to an AC network, the converter including at least one switching element; a circuit interruption device operably connected to the AC side of the converter; a DC voltage modification device operably connected to the DC side of the converter, the DC voltage modification device including a DC chopper; and a controller configured to selectively control the or each switching element, the circuit interruption device and the DC voltage modification device, wherein the controller is configured to be responsive to a converter internal fault by carrying out a fault operating mode.

Abstract: Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.