Patents by Inventor Chandra Mohan

Chandra Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11398414
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Pooya Tadayon, Joe F. Walczyk, Chandra Mohan Jha, Weihua Tang, Shrenik Kothari, Shankar Devasenathipathy
  • Publication number: 20220222105
    Abstract: System and techniques for container provisioning are described herein. A request to instantiate a container image may be made. This request specifies a name for the container image where the name is created through a first defined generation process applied to contents of the container image. A container manifest may be received from a local copy of a distributed container directory. The container manifest includes a set of entries for container layer images of the container image. Here, the set of entries are named by a second defined generation process applied to respective container layer images. Then, container layer images may be retrieved using names from the set of entries and the container image instantiated using the retrieved container layer images.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Jeffrey Christopher Sedayao, Juan Pablo Munzo, Vinoth kumar Chandra Mohan, Promila Agarwal, Dean Chu, Eve M. Schooler, Kshitij Arun Doshi
  • Patent number: 11387224
    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Chandra Mohan M Jha, Ying Wang, Kyu-oh Lee
  • Publication number: 20220143140
    Abstract: The present disclosure provides methods of treating inflammatory or autoimmune diseases (e.g., lupus nephritis) using CD6-ALCAM pathway inhibitors such as EQ001 and to methods and diagnostic tests for identifying subjects likely to respond to such inhibitors. In particular, the present disclosure provides diagnostic and therapeutic uses related to elevated levels of soluble ALCAM and/or CD6 protein and protein fragments in urine and other biological samples that are indicative of sensitivity to inhibitors of the CD6-ALCAM pathway (e.g., EQ001).
    Type: Application
    Filed: February 26, 2020
    Publication date: May 12, 2022
    Inventors: Stephen Connelly, Krishna Polu, Chandra Mohan
  • Publication number: 20220147533
    Abstract: Embodiments of a computer-implemented system and methods for automated ranking of computer element/asset importance are disclosed.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 12, 2022
    Inventors: Paulo Shakarian, Jana Shakarian, Chandra Mohan
  • Publication number: 20220109364
    Abstract: A converter (20) comprises: a first terminal and a second terminal (24,26), the first terminal (24,26) configured for connection to a first network, the second terminal (34) configured for connection to a second network (40); at least one switching module (44) arranged to interconnect the first terminal (24,26) and the second terminal (34), the or each switching module (44) including at least one module switching element (46) and at least one energy storage device (48), the or each module switching element (46) and the or each energy storage device (48) in the or each switching module (44) arranged to be combinable to selectively provide a voltage source, the or each switching module (44) switchable to control a transfer of power between the first and second networks (40); the or each switching module (44) including a discharge circuit, the or each discharge circuit including a discharge switching element (50) and a discharge resistor (52), the or each discharge switching element (50) switchable to switch
    Type: Application
    Filed: March 7, 2019
    Publication date: April 7, 2022
    Inventors: Chandra Mohan Sonnathi, Radnya Anant Mukhedkar, Rajaseker Reddy Ginnareddy
  • Patent number: 11290422
    Abstract: Systems and methods include, responsive to routing a packet to a destination via an external interface of a plurality of external interfaces, receiving the packet; checking if the packet belongs to an existing session for network address and port translation based on a session key; if the packet does not belong to the existing session, assigning the packet an Internet Protocol (IP) address and port based on the routing; if the packet belongs to the existing session, checking if an active path has changed, and, if not, performing the network address and port translation based on the session; and, if the active path has changed, assigning the packet an Internet Protocol (IP) address and port based on another external interface associated with the changed active path.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Ciena Corporation
    Inventors: Vijay Mohan Chandra Mohan, Prasanth Gajarampalli
  • Publication number: 20220024308
    Abstract: A method and a system of deploying an ignition interlock device (IID). The method comprises receiving a time series of breath alcohol content (BrAC) measurements that are unitarily sourced from a pre-identified user, each BrAC measurement of the time series including an alveolar breath component and an interferent breath component; estimating a dissipation rate of alcohol attributable to the pre-identified user in accordance with the time series of BrAC measurements; determining, responsive to estimating the dissipation rate of alcohol, at least a subset of the BrAC measurements as being based on the alveolar breath component but not the interferent breath component; and performing one of triggering and not triggering the IID into a lockout state based on the at least a subset of the BrAC measurements.
    Type: Application
    Filed: July 27, 2020
    Publication date: January 27, 2022
    Inventors: Amanda Renee Mallinger, Jennifer Ringgenberg, Usha Rani Chintala, Douglas Robert Bruce, Sujitha Chandra Mohan
  • Publication number: 20210391244
    Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Chandra Mohan JHA, Pooya TADAYON, Aastha UPPAL, Weihua TANG, Paul DIGLIO, Xavier BRUN
  • Publication number: 20210359617
    Abstract: There is provided an electrical assembly (20) for interconnecting first and second networks (40).
    Type: Application
    Filed: March 20, 2019
    Publication date: November 18, 2021
    Inventors: Chandra Mohan Sonnathi, Radnya Anant Mukhedkar, Rajaseker Reddy Ginnareddy, Amit Kumar, Damien Pierre Gilbert Fonteyne
  • Publication number: 20210280497
    Abstract: A modular technique for die-level liquid cooling is described. In an example, an integrated circuit assembly includes a first silicon die comprising a device side and a backside opposite the device side. The integrated circuit assembly also includes a second silicon die comprising a plurality of fluidly accessible channels therein. A dielectric interface directly couples the second silicon die to a backside of the first silicon die.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Xavier F. BRUN, Chandra Mohan JHA
  • Patent number: 11106627
    Abstract: A system, method and the like for front-end comprehensive validation of data files that require processing by multiple different computing systems having different validation requirements. Validation for all of the multiple different computing systems is performed upon receipt of the data file by the data processing entity and, as such, in the event that validation results in an error/failure, the originator/sender of the data file can be notified of the error failure proximate in time to when the data file is transmitted to the data processing entity and can re-submit a valid data file in due time. In addition, the present invention is configured to insure that the validation meets the current requirements of all the computing systems that process the data file by employing a centralized data file validation requirements database that stores validation requirements for each of the computing systems.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: August 31, 2021
    Assignee: BANK OF AMERICA CORPORATION
    Inventor: Mahesh Chandra Mohan
  • Publication number: 20210249324
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventors: Zhimin WAN, Chia-Pin CHIU, Chandra Mohan JHA
  • Publication number: 20210193547
    Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Zhimin WAN, Chandra Mohan JHA, Je-Young CHANG, Chia-Pin CHIU, Liwei WANG
  • Publication number: 20210193549
    Abstract: Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Feras EID, Chandra Mohan JHA, Je-Young CHANG
  • Publication number: 20210125897
    Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Krishna Vasanth VALAVALA, Ravindranath V. MAHAJAN, Chandra Mohan JHA
  • Publication number: 20210119444
    Abstract: The present invention provides a high voltage direct current (HVDC) transmission system (300, 600) comprising: a first station (102) comprising series-connected first and second HVDC converters (110, 130); a second station (104) comprising series-connected third and fourth HVDC converters (150, 170), wherein a neutral node (164) coupling the third HVDC converter (150) to the fourth HVDC converter (170) is coupled to earth; a first transmission line (200) connecting a positive node (114) of the first HVDC converter (110) to a corresponding positive node (154) of the third HVDC converter (150), wherein a first pole (240) of the system (300, 600) comprises the first HVDC converter (110), the third HVDC converter (150) and the first transmission line (200); a second transmission line (210) connecting a negative node (138) of the second HVDC converter (130) to a corresponding negative node (178) of the fourth HVDC converter (170), wherein a second pole (250) of the system (300, 600) comprises the second HVDC conve
    Type: Application
    Filed: April 11, 2019
    Publication date: April 22, 2021
    Inventors: Chandra Mohan SONNATHI, Radnya Anant MUKHEDKAR, Jordann Raymond Martial BRIONNE, Damien Pierre Gilbert FONTEYNE
  • Publication number: 20210118756
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Inventors: Zhimin WAN, Chandra Mohan JHA, Je-Young CHANG, Chia-Pin CHIU
  • Publication number: 20210105348
    Abstract: Disclosed are a system, method and devices for simultaneous MACsec key agreement (MKA) negotiation between the devices. The present application controls a basic TLV message exchange between supplicant and authenticator in case of race condition to establish the secure association key (SAK) channel. The present application by controlling a basic TLV message exchange enables to establish a secure channel in race condition and achieves a high reliability of the product as this makes product launch MACsec services quickly and available for the service. Accordingly, when both sides (two supplicants) exchange hello with basic TLV at the same time, triggering the race condition, drops first message from the authenticator at supplicant and update the peer MN and the supplicant will not send reply. The authenticator when send next message (basic+potential peer TLV) with peer MN incremented by 1, the supplicant will respond with incremental message with live peer TLV.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Dharmanandana Reddy Pothula, Chandra Mohan Padamati, Antony Paul, Yun Qin, De Sheng
  • Publication number: 20210104448
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a lateral heat spreader (LHS) over a package substrate, and a first die over the LHS and package substrate. The first die has a first region and a second region, where the first and second regions are on a bottom surface of the first die. The semiconductor package includes a plurality of second dies over the first die, and an integrated heat spreader (IHS) over the second dies, first die, LHS, and package substrate. The IHS includes a lid and legs. The LHS thermally couples the first region of the first die to the legs of the IHS, and laterally extends from below the first region of the first die to below the legs of the IHS. The LHS may be comprised of graphene sheets, heat pipes, or vapor chambers and coupled to a thermal conductive material and a sealant.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Feras EID, Chandra Mohan JHA, Je-Young CHANG