Patents by Inventor Chang-An Hsieh

Chang-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thickening phase for spin coating process
    Patent number: 9360755
    Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Wei Chang, Chia-Chieh Lin, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
  • Large-area plasma generating apparatus
    Patent number: 9355821
    Abstract: A large-area plasma generating apparatus is disclosed, which includes a reaction chamber; a first electrode disposed in the reaction chamber; a second electrode parallel with the first electrode and disposed in the reaction chamber; and a discharge region formed between the first and second electrodes and a plasma can be formed therein; wherein a travelling wave or a traveling-wave-like electromagnetic field is generated via at least one of the first and second electrodes and travels from one end of the discharge region to its opposite end, so as to uniform the plasma in the discharge region.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 31, 2016
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Hsin-Liang Chen, Cheng-Chang Hsieh, Deng-Lain Lin, Yan-Zheng Du, Chi-Fong Ai, Ming-Chung Yang
  • Test structure placement on a semiconductor wafer
    Patent number: 9349662
    Abstract: A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Ling Wu, Cheng-Hsien Chuang, Chun-Chang Chen, Wang-Pen Mo, Hung-Chang Hsieh
  • Method of Forming Source/Drain Contact
    Publication number: 20160118303
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 28, 2016
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • COMPOSITE POWDER OF CARBIDE/BLENDING METAL
    Publication number: 20160115572
    Abstract: A composite powder is provided. The composite powder comprises 80-97 wt % of carbide and 3-20 wt % of blending metal powder comprising cobalt and a first metal powder, wherein the first metal powder is formed of one of aluminum, titanium, iron, nickel, or a combination thereof, and the amount of cobalt is 90-99% of total blending metal powder.
    Type: Application
    Filed: January 8, 2015
    Publication date: April 28, 2016
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-San CHEN, Chih-Chao YANG, Lik-Hang CHAU, Ching-Chang HSIEH, Yen-Yu HOU
  • Memory array and operating method of same
    Patent number: 9305653
    Abstract: A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 5, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Kuo-Pin Chang, Hang-Ting Lue
  • System and method for lithography alignment
    Patent number: 9304403
    Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
  • Operation method for memory device
    Patent number: 9305638
    Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 5, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Yung-Chun Li, Chih-Chang Hsieh, Shih-Fu Huang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • VACUUM COATING APPARATUS
    Publication number: 20160076143
    Abstract: A vacuum coating apparatus includes at least a chamber, an arc discharge plasma source, a feeding-reeling unit, and a roller set. The first and second openings are connecting with the feeding or reeling unit so as to allow the substrate to enter and leave the chamber therethrough, respectively. The arc discharge plasma source located inside the chamber generates the plasma, which discharges radially from the arc discharge plasma source as its center. The roller set includes a plurality of the first rollers, which are located in the chamber and enclosing the arc discharge plasma source. A first surface of the substrate is facing the plurality of the first rollers and contacts tightly on the periphery of the first rollers so that the first rollers can rotate by the moving of the substrate. The material evaporated and emitted by the plasma is attached onto the first surface of the substrate.
    Type: Application
    Filed: August 7, 2015
    Publication date: March 17, 2016
    Inventors: Cheng-Chang HSIEH, Deng-Lian LIN, En-Shih CHEN, Wen-Fa TSAI, Chi-Fong AI
  • Lithography process on high topology features
    Patent number: 9285677
    Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Chang, Hong-Da Lin, Chih-Chien Wang, Chun-Chang Chen, Wang-Pen Mo, Hung-Chang Hsieh
  • CLIP FOR CLAMPING ELECTRONIC COMPONENT
    Publication number: 20160073549
    Abstract: A clip for clamping an electronic device includes a main body and a plurality of claws. Each claw extends outwardly from an edge of the main body, and each claw has a clamping portion formed on the claw for abutting and connecting the electronic device, and clamping portions are arranged on at least two different planes, so that different claws produce appropriate clamping forces at different clamping positions respectively.
    Type: Application
    Filed: December 31, 2014
    Publication date: March 10, 2016
    Inventors: Hsi-An LIU, Hung-Chang HSIEH, Shih-Ming YAN
  • Cross quadrupole double lithography method using two complementary apertures
    Patent number: 9280041
    Abstract: A method of photolithography including coupling a first aperture to a lithography system, then performing a first illumination process to form a first pattern on a layer of a substrate using the first aperture, thereafter coupling a second aperture to the lithography system, and performing a second illumination process to form a second pattern on the layer of the substrate using the second aperture. The first aperture includes a first pair and a second pair of radiation-transmitting regions. The second aperture includes a second plate having a third pair and a fourth pair of radiation-transmitting regions.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Cheng Wang, Hung Chang Hsieh, Shih-Che Wang, Ping Chieh Wu, Wen-Chun Huang, Ming-Chang Wen
  • ANTENNA APPARATUS AND THE MIMO COMMUNICATION DEVICE USING THE SAME
    Publication number: 20160049736
    Abstract: The present invention discloses an antenna apparatus. The antenna apparatus includes a first antenna array and a second antenna array. The first antenna array includes multiple first radiating elements for transmitting radio signals of a first frequency. The second antenna array includes multiple second radiating elements for transmitting radio signals of a second frequency, wherein the first and second radiating elements are arranged in a staggered manner; wherein each of the first radiating elements is disposed between two of the second radiating elements; and wherein each of the second radiating elements is disposed between two of the first radiating elements.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 18, 2016
    Applicant: ACCTON TECHNOLOGY CORPORATION
    Inventors: I-Ru LIU, Chih-Chang HSIEH, Yi-Chang CHEN, Yang-Te FU, Chang-Cheng LIU, Chun-Teng HSU
  • Method of Semiconductor Integrated Circuit Fabrication
    Publication number: 20160027692
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Integrated circuit and operating method for the same
    Patent number: 9245603
    Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 26, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Yen-Hao Shih, Chih-Chang Hsieh, Chih-Wei Hu
  • Testing method and testing apparatus for testing function of electronic apparatus
    Patent number: 9183115
    Abstract: A method for testing a function of an electronic apparatus is provided. The method includes steps of: searching for a location corresponding to the function to be tested, sending a command according to the location to perform the function to be tested, and determining whether an error occurs in the function according to a response from the function in response to the command.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 10, 2015
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yi-Cheng Lin, Shen-Pin Lin, Chi-Chang Hsieh, Wei-Chun Kao
  • Method and apparatus for drying a wafer
    Patent number: 9176387
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Huang, Hung Chang Hsieh
  • Method of overlay prediction
    Patent number: 9158209
    Abstract: A method includes receiving a substrate having a material feature embedded in the substrate, wherein receiving the substrate includes receiving a first leveling data and a first overlay data generated when forming the material feature, deposing a resist film on the substrate, and exposing the resist film using a predicted overlay correction data to form a resist pattern overlying the material feature on the substrate, wherein using the predicted overlay correction data includes generating a second leveling data and calculating the predicted overlay correction data using the first leveling data, the first overlay data, and the second leveling data.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Jui Chen, Fu-Jye Liang, Hung-Chang Hsieh
  • Method and system for repairing wafer defects
    Patent number: 9158884
    Abstract: A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method can further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between the repeating defects. A distance between a first focal point and a second focal point of a lithographic system can be configured to correspond to the spacing between the repeating defects. Thus, a first repeating defect and a second repeating defect can be repaired concurrently.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Hung-Chang Hsieh
  • WATER-REPELLENT EARPHONE
    Publication number: 20150289051
    Abstract: A water-repellent earphone is formed of a main body and a water-repellent breathable member. The main body includes a receiving space for accommodating a speaker. The speaker partitions the receiving space to make a rear chamber. The main body includes a drainage tunnel communication with a first opening and a second opening, both of which are located on an external surface of the main body. The main body further includes a venthole communicating with the drainage tunnel and the rear chamber. The water-repellent breathable member is formed and located at the venthole. In light of the structure mentioned above, the drainage tunnel can help the earphone quickly expel the moisture to prevent the moisture from damage to the speaker and to boost the frequency response and acoustic performance within the low-frequency range.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: MERRY ELECTRONICS (SHENZHEN) CO., LTD.
    Inventors: Chiu-Yun TUNG, Fang-Chang HSIEH, Yu-Chang FAN, Chien-Cheng YANG