Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m-1.

Abstract: Systems, methods, and devices for providing an operational dashboard are described herein. One method includes receiving operational data associated with a system, receiving credentials associated with a user of a user device including a number of display elements configurable by the user, and determining a particular portion of the operational data to provide to the user via the display elements of the user device based, at least in part, on the credentials.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

Abstract: A mask substrate, photomask and method for forming the same are provided. The photomask includes a substantially light transparent substrate and a circuitry pattern disposed over the light transparent substrate. The circuitry pattern includes a phase shifting layer disposed over the substantially light transparent substrate. A substantially light shielding layer is disposed over the phase shifting layer. At least one barrier layer is disposed over the substantially light shielding layer. An uppermost portion of the substantially light shielding layer does not comprise anti-reflective properties and the at least one barrier layer comprises an uppermost hardmask layer and an underlying anti-reflective layer.

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract: The invention relates to an electronic component with Sn rich deposit layer on the part for electric connection, wherein the Sn rich deposit layer is a fine grained Sn rich deposit layer composed of grains with smaller size in the direction perpendicular to the deposit surface than in the direction parallel to the deposit surface. It also relates to a process for plating an electronic component, so as to form a Sn rich deposit layer on the part for electric connection, comprising the steps of: adjusting the composition of tin plating solution in which starter additive and brighter additive are included; moving the electronic component through the tin plating solution, so as to form a fine grained Sn rich deposit layer on the part for electric connection. As compared with the prior art, the invention can validly inhibit the whisker growth with low cost and reliable property.

Abstract: A method is described including forming a first photoresist feature and a second photoresist feature on a semiconductor substrate. A chemical material coating is formed on the semiconductor substrate. The chemical material coating interposes the first and second photoresist features. The semiconductor substrate is then rinsed; the rinsing removes the chemical material coating from the semiconductor substrate. The chemical material may mix with a residue disposed on the substrate between the first and second photoresist features. Removing the chemical material coating from the substrate may also remove the residue.

Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.

Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.

Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.

Abstract: A method for estimating an operational parameter of a motor is to be implemented by an estimating device. In the method, the estimating device is configured to: receive an acoustic signal attributed to operation of the motor; process the acoustic signal to obtain a plurality of sample points in the frequency domain, each of which has a frequency and a corresponding amplitude; compute an estimated peak frequency using a centroid method based upon the frequencies and the amplitudes; from a plurality of peak frequencies and a plurality of known values of the operational parameter corresponding respectively to the peak frequencies, select a part of the peak frequencies approximate to the estimated peak frequency and a corresponding part of the known values of the operational parameter; and compute an estimated value of the operational parameter based upon the peak frequencies and the known values of the operational parameter.

Abstract: An earphone device with a bass adjusting function is provided. The earphone device includes an accommodating portion and an extension segment. The accommodating portion has an inner chamber for accommodating a speaker. The extension segment which is hollow-shaped and has a first space and a second space therein, and the first space is in communication with the inner chamber of the accommodating portion, and when a portion of the extension segment is adjusted from a first position to a second position, the first space, the second space, and the inner chamber of the accommodating portion are in communication, so as to increase a volume of the back chamber of the speaker.

Abstract: A light-emitting diode (LED) device includes at least one LED unit. Each LED unit includes at least one LED. Each LED includes an n-side nitride semiconductor layer, a p-side nitride semiconductor layer, and an active layer that is located between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer. The active layer is includes one or more well layers. At least one of the well layers has a multilayered structure.

Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated.

Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.