Patents by Inventor Chang-An Hsieh

Chang-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for fabricating semiconductor devices having larger die dimensions
    Patent number: 9006040
    Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chang Hsieh, Kong-Beng Thei
  • Integrated circuit layout and method with double patterning
    Patent number: 8987008
    Abstract: The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tsai-Sheng Gau, Yao-Ching Ku
  • DESIGN STRUCTURE FOR CHIP EXTENSION
    Publication number: 20150082265
    Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Inventors: Chin-Min Huang, Chia-Cheng Chang, Cherng-Shyan Tsay, Chien-Wen Lai, Kong-Beng Thei, Hua-Tai Lin, Hung-Chang Hsieh
  • Method of manufacturing a semiconductor apparatus
    Patent number: 8980728
    Abstract: A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the first-type doped layer and the second-type doped layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Phostek, Inc.
    Inventors: Yen-Chang Hsieh, Jinn Kong Sheu, Heng Liu, Chun-Chao Li, Ya-Hsuan Shih, Chia-Nan Chen
  • Method of making a FinFET device
    Patent number: 8975129
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a fine cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Chen-Yu Chen
  • Method For Integrated Circuit Patterning
    Publication number: 20150064916
    Abstract: A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tien-I Bao, Chung-Ju Lee, Shau-Lin Shue
  • Structure for chip extension
    Patent number: 8972912
    Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Min Huang, Chia-Cheng Chang, Cherng-Shyan Tsay, Chien-Wen Lai, Kong-Beng Thei, Hua-Tai Lin, Hung-Chang Hsieh
  • INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING
    Publication number: 20150056724
    Abstract: The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tsai-Sheng Gau, Yao-Ching Ku
  • Semiconductor apparatus
    Patent number: 8963297
    Abstract: A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the p-type doped layer and the n-type doped layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: February 24, 2015
    Assignee: Phostek, Inc.
    Inventors: Yen-Chang Hsieh, Jinn Kong Sheu, Heng Liu, Chun-Chao Li, Ya-Hsuan Shih, Chia-Nan Chen
  • Metal grid in backside illumination image sensor chips and methods for forming the same
    Patent number: 8940574
    Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Wang, Chu-Wei Chang, Wang-Pen Mo, Hung-Chang Hsieh
  • LARGE-AREA PLASMA GENERATING APPARATUS
    Publication number: 20140375207
    Abstract: A large-area plasma generating apparatus is disclosed, which includes a reaction chamber; a first electrode disposed in the reaction chamber; a second electrode parallel with the first electrode and disposed in the reaction chamber; and a discharge region formed between the first and second electrodes and a plasma can be formed therein; wherein a travelling wave or a traveling-wave-like electromagnetic field is generated via at least one of the first and second electrodes and travels from one end of the discharge region to its opposite end, so as to uniform the plasma in the discharge region.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: HSIN-LIANG CHEN, CHENG-CHANG HSIEH, DENG-LAIN LIN, YAN-ZHENG DU, CHI-FONG AI, MING-CHUNG YANG
  • Method of making a lithography mask
    Patent number: 8916482
    Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen
  • FRAMEWORKS, DEVICES AND METHODS CONFIGURED FOR ENABLING GESTURE-BASED CONTROLLED DISPLAY FOR FACILITY INFORMATION AND CONTENT IN RESPECT OF A MULTI-LEVEL FACILITY
    Publication number: 20140365976
    Abstract: Described herein are frameworks, devices and methods configured for enabling display for facility information and content, in some cases via touch/gesture controlled interfaces. Embodiments of the invention have been particularly developed for allowing an operator to conveniently access a wide range of information relating to a facility via, for example, one or more wall mounted displays. While some embodiments will be described herein with particular reference to that application, it will be appreciated that the invention is not limited to such a field of use, and is applicable in broader contexts.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 11, 2014
    Inventors: John D. Morrison, Graeme Laycock, Yi-Chang Hsieh
  • Providing an operational dashboard
    Patent number: 8904497
    Abstract: Systems, methods, and devices for providing an operational dashboard are described herein. One method includes receiving operational data associated with a system, receiving credentials associated with a user of a user device including a number of display elements configurable by the user, and determining a particular portion of the operational data to provide to the user via the display elements of the user device based, at least in part, on the credentials.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: December 2, 2014
    Assignee: Honeywell International Inc.
    Inventor: Yi-Chang Hsieh
  • Enclosure for image capture systems with focusing capabilities
    Patent number: 8896743
    Abstract: Embodiments of the invention describe an enclosure for an image capture system that includes an image capture unit and a solid state die to provide focusing capabilities for a lens unit of the image capture unit. The enclosure may electrically couple the solid state die to the image capture unit and/or other system circuitry. The enclosure may further serve as EMI shielding for the image capture system.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 25, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Zheng Du, Denis Chu, Yi-Chang Hsieh, Wei-Feng Lin, Wen-Jen Ho
  • Method of semiconductor integrated circuit fabrication
    Patent number: 8883403
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chang Chen, Shun-Shing Yang, Chuan-Ling Wu, Wang-Pen Mo, Hung-Chang Hsieh
  • THICKENING PHASE FOR SPIN COATING PROCESS
    Publication number: 20140272704
    Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Chun-Wei Chang, Chia-Chieh Lin, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
  • SEMICONDUCTOR APPARATUS WITH TRANSPORTABLE EDGE RING FOR SUBSTRATE TRANSPORT
    Publication number: 20140273505
    Abstract: An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.
    Type: Application
    Filed: April 9, 2013
    Publication date: September 18, 2014
    Inventors: Chih-Chang HSIEH, Yung-Kai Lin, Hsu-Shui Liu, Kai Lo, Chih-Ping Chen, Chian-Kun Chan, Chung-Chieh Hsu, Chih-Kuo Chang, Wei-Ting Hsiao
  • Systems and Methods for Fabricating Semiconductor Devices Having Larger Die Dimensions
    Publication number: 20140264823
    Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.
    Type: Application
    Filed: April 16, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Ming-Chang Hsieh, Kong-Beng Thei
  • Lithography System with an Embedded Cleaning Module
    Publication number: 20140268074
    Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.
    Type: Application
    Filed: January 30, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen