Patents by Inventor Chang-An Hsieh
Chang-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140272715Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.Type: ApplicationFiled: November 5, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Chang, Hong-Da Lin, Chih-Chien Wang, Chun-Chang Chen, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 8828843Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.Type: GrantFiled: May 2, 2013Date of Patent: September 9, 2014Assignee: Inotera Memories, Inc.Inventors: Yaw-Wen Hu, Jung-Chang Hsieh, Kuen-Shin Huang, Jian-Wei Chen, Ming-Tai Chien
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Publication number: 20140220762Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.Type: ApplicationFiled: May 2, 2013Publication date: August 7, 2014Applicant: INOTERA MEMORIES, INC.Inventors: YAW-WEN HU, JUNG-CHANG HSIEH, KUEN-SHIN HUANG, JIAN-WEI CHEN, MING-TAI CHIEN
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Publication number: 20140198576Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.Type: ApplicationFiled: March 14, 2013Publication date: July 17, 2014Applicant: MACRONIX INTERNATIONAL CO, LTD.Inventors: Shuo-Nan Hung, HANG-TING LUE, TI-WEN CHEN, SHIH-LIN HUANG, KUO-PIN CHANG, CHIH-CHANG HSIEH, CHUN-HSIUNG HUNG
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Publication number: 20140198570Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.Type: ApplicationFiled: January 13, 2014Publication date: July 17, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHIH-CHANG HSIEH, TI-WEN CHEN, YUNG CHUN LI, KUO-PIN CHANG
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Patent number: 8778080Abstract: Disclosed is an atmospheric-pressure double-plasma graft polymerization apparatus. The apparatus includes a workbench, an initial roller of a roll-to-roll device, an atmospheric-pressure plasma activation device, a peroxide formation device, a coating and grafting device, a drying device, a graft polymerization and curing device, a curing device and a final roller of a roll-to-roll device. The devices are sequentially provided on the workbench.Type: GrantFiled: May 21, 2008Date of Patent: July 15, 2014Assignee: Institute of Nuclear Energy Research, Atomic Energy CouncilInventors: Mien-Win Wu, Tien-Hsiang Hsueh, Cheng-Chang Hsieh, Chi-fong Ai
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Publication number: 20140190634Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated.Type: ApplicationFiled: January 21, 2014Publication date: July 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chieh Huang, Hung Chang Hsieh
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Patent number: 8771534Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.Type: GrantFiled: January 13, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chang Chen, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
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Publication number: 20140185025Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Patent number: 8760928Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.Type: GrantFiled: December 11, 2012Date of Patent: June 24, 2014Assignee: Macronix International Co. Ltd.Inventors: Ti-Wen Chen, Hang-Ting Lue, Shuo-Nan Hung, Shih-Lin Huang, Chih-Chang Hsieh, Kuo-Pin Chang
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Publication number: 20140151699Abstract: A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Ling Wu, Cheng-Hsien Chuang, Chun-Chang Chen, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 8729939Abstract: A charging/discharging circuit includes a connection terminal, a reference current providing module, an up current module and a down current module. The down current module includes: a first switch module, having a first control terminal, for receiving the down signal to determine whether the first switch module is turned on; a first bias transistor, having a first terminal coupled to the connection terminal, a second terminal coupled to the first switch module, and a control terminal coupled to the reference current providing module; and a first capacitor simulation transistor, having a first terminal and a second terminal coupled to the control terminal of the first switch module, and a control terminal coupled to the control terminal of the first bias transistor.Type: GrantFiled: August 21, 2013Date of Patent: May 20, 2014Assignee: MStar Semiconductor, Inc.Inventor: Yi Chang Hsieh
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Publication number: 20140125370Abstract: A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head.Type: ApplicationFiled: March 6, 2013Publication date: May 8, 2014Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Shih-Duen Lin, Wen-Jen Ho, Chih-Pin Jen, Wei-Feng Lin, Yi-Chang Hsieh
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Publication number: 20140111779Abstract: A method includes receiving a substrate having a material feature embedded in the substrate, wherein receiving the substrate includes receiving a first leveling data and a first overlay data generated when forming the material feature, deposing a resist film on the substrate, and exposing the resist film using a predicted overlay correction data to form a resist pattern overlying the material feature on the substrate, wherein using the predicted overlay correction data includes generating a second leveling data and calculating the predicted overlay correction data using the first leveling data, the first overlay data, and the second leveling data.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: TAIWAN SEMECONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Jui Chen, Fu-Jye Liang, Hung-Chang Hsieh
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Patent number: 8703403Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated.Type: GrantFiled: December 22, 2011Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Huang, Hung Chang Hsieh
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Publication number: 20140102368Abstract: A gas isolation chamber comprises a vacuum chamber, a first body module, a second body module and a first temperature modulator. The vacuum chamber comprises a first chamber part, a second chamber part and at least one first gas valve unit. The first body module is disposed on the inner wall of the first chamber part and has a first gas hole corresponding to the position of the first gas valve unit. The first gas hole is connected to the first gas valve unit. The second body module is disposed on the inner wall of the second chamber part such that a slit channel can be formed between the second and the first body modules. The first temperature modulator is disposed in the first body module. The gas isolation chamber is further combined with the vacuum film process chambers to form a plasma deposition apparatus for proceeding continuous deposition process.Type: ApplicationFiled: May 31, 2013Publication date: April 17, 2014Inventors: CHENG-CHANG HSIEH, DENG-LAIN LIN, CHING-PEI TSENG, JIN-YU WU, JIUN-SHEN CHEN, CHI-FONG AI
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Patent number: 8692296Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.Type: GrantFiled: February 9, 2012Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chang Chen, Shun-Shing Yang, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
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Publication number: 20140078804Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: Macronix International Co., Ltd.Inventors: Chih-Chang Hsieh, Shih-Hung Chen, Hang-Ting Lue
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Publication number: 20140080067Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chang Chen, Shun-Shing Yang, Chuan-Ling Wu, Wang-Pen Mo, Hung-Chang Hsieh
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Publication number: 20140074309Abstract: A power usage control system includes a transmission medium for transmitting power. A management module is coupled to the transmission medium. A control module is coupled to the transmission medium and at least one controlled apparatus. The management module and the control module communicate with each other through the transmission medium. The management module monitors an operation status of the at least one controlled apparatus through the control module. The management module controls the at least one controlled apparatus through the control module.Type: ApplicationFiled: September 10, 2012Publication date: March 13, 2014Inventors: Rong-Ching Wu, Chun-Wei Tseng, Chun-Hui Ho, Chiung-Chang Hsieh
