Patents by Inventor Chang-Lin (Peter) Hsieh

Chang-Lin (Peter) Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12034062
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Patent number: 12033331
    Abstract: A method for detecting motion information includes the following steps. First, a pixel array is provided for detecting an image of a measured object located in a first distance range or in a second distance range, and the pixel array includes a plurality of invisible image sensing pixels and a plurality of visible image sensing pixels. Then, image detection is conducted within the first distance range by using the invisible image sensing pixels to output a plurality of invisible images. Next, the image detection is conducted within the second distance range by using the visible image sensing pixels to output a plurality of visible images. Then, the plurality of invisible images and the plurality of visible images are analyzed by using a processing unit, so as to obtain motion information of the measured object. A pixel array for detecting motion information and an image sensor are also provided.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 9, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Han-Chang Lin, Shu-Sian Yang, Shih-Feng Chen
  • Publication number: 20240223058
    Abstract: An industrial heavy load electric linear actuator includes a gearbox, an electric motor, a lead screw, an extension pipe and a load baring structure. The electric motor is connected to the gearbox. A portion of the lead screw is received inside the gearbox and driven by the electric motor, and another portion of the lead screw is extended out of the gearbox. The extension pipe is movably fastened to the lead screw. The load bearing structure includes a sleeve, a bearing, a fastening element, a fixation seat, and a rear supporting seat. The sleeve is mounted to the lead screw and holds the bearing jointly with the fastening element. The fixation seat and the rear supporting seat hold the bearing at outer perimeters of the sleeve and the fastening element.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventor: Yu-Chang LIN
  • Publication number: 20240219332
    Abstract: An electrical impedance imaging sensing system includes a signal processing device, a sensing element and a processor. The signal processing device is electrically coupled to the sensing element and configured for outputting an emission signal. Each of N electrodes of the sensing element is configured to receive a received signal after the emission signal passes through a to-be tested object. The processor is configured to determine whether one of the N electrodes fails according to a plurality of the received signal; in response to the failure of the electrode, compensate the received signal of the failed electrode; and generate an electrical impedance image pre-processing data according to the received signal.
    Type: Application
    Filed: December 12, 2023
    Publication date: July 4, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Lin HU, Zong-Yan LIN, I-Cheng CHENG, Chien-Ju LI, Chii-Wann LIN
  • Patent number: 12025171
    Abstract: A tamper-proof screw includes a main body, a pin body, a ball, and at least one abutting member. A through hole is provided in the main body. The pin body is movably disposed in the through hole. The ball is located in the through hole. The abutting member is located in the through hole and has a connecting end and a free end opposite to each other. The connecting end is disposed on an inner wall of the main body and located between the ball and the free end. The ball is located between the pin body and the abutting member. When the pin body moves in the through hole to push the ball to press against the connecting end of the abutting member, the abutting member pivots around the connecting end to allow the free end to extend outwards from the main body.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: July 2, 2024
    Assignees: MAINTEK COMPUTER (SUZHOU) CO., LTD, PEGATRON CORPORATION
    Inventor: Chang-Lin Zhang
  • Patent number: 12021082
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 12014992
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
  • Publication number: 20240194758
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
  • Patent number: 12009912
    Abstract: An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Stefan Rusu, Weiwei Song, Lan-Chou Cho
  • Patent number: 12009253
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 12009611
    Abstract: A thin type lock and unlock connector include a first shell, a second shell and a first insulator, which are buckled and combined with each other by the respective provided first fixing members to form a connector that can be connected to a flexible printed circuit board. The second shell provides a first locking member and a first elastic member to lock the flexible printed circuit board to the connector. When an external force is applied to the first pressing part of the first shell, it acts on the locking member to unlock the flexible printed circuit board that the flexible printed circuit board can be detached from the connector. The first insulator provides an action portion with a slope to be arranged corresponding to the first locking member, to determine the deformation stroke of the first locking member.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: June 11, 2024
    Assignee: P-TWO INDUSTRIES INC.
    Inventor: Hsien-Chang Lin
  • Patent number: 12009410
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 12010924
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Pin Chiu, Chang-Lin Yang, Chien-Hua Huang, Chen-Chiu Huang, Chih-Fan Huang, Dian-Hau Chen
  • Publication number: 20240178745
    Abstract: An alternating current control system includes a zero crossing detector, an alternating current solid state relay, a constant current driver, and a microcontroller connected to the zero crossing detector and the constant current driver. The zero crossing detector and the alternating current solid state relay are connected to an alternating current power source, a first control pin of the microcontroller receives a zero crossing detection signal outputted by the zero crossing detector, a second control pin of the microcontroller receives a switch state signal, and a third control pin of the microcontroller is connected to the constant current driver and outputs a control signal. Based on the switch state signal and the zero crossing detection signal, the microcontroller adjusts a level of the control signal and controls an electrical connection between the alternating current solid state relay and the alternating current power source.
    Type: Application
    Filed: March 16, 2023
    Publication date: May 30, 2024
    Inventors: Hui-Chiang Yang, CHIA-CHANG LIN
  • Patent number: 11996293
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 11997888
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 28, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Sheng-Yu Chen, Chang-Lin Yeh, Yung-I Yeh
  • Patent number: 11996482
    Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao
  • Publication number: 20240170556
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.
    Type: Application
    Filed: February 20, 2023
    Publication date: May 23, 2024
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20240165262
    Abstract: Provided is a toroidal mixed nanoparticle including a first polymer and a second polymer interacting with the first polymer. Also provided is a method for preparing the toroidal mixed nanoparticle, including mixing the first polymer and the second polymer having cleavable hydrophobic groups to form a mixed nanoparticle; and removing a portion of cleavable hydrophobic groups from the second polymer to make the second polymer charged and to form the toroidal mixed nanoparticle. Further provided is a method for delivering a drug or a bioactive agent to a subject in need thereof, including administering to the subject a pharmaceutical composition that includes the toroidal mixed nanoparticle conjugated to an effective amount of the drug or the bioactive agent, and a pharmaceutically acceptable excipient thereof.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Inventors: YI-TING CHIANG, HUI-CHANG LIN, GUAN-JHONG HUANG