Patents by Inventor Chang-Lin (Peter) Hsieh

Chang-Lin (Peter) Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IMAGE RECOGNITION SYSTEM, SENSOR MODULE, AND METHOD FOR IMAGE RECOGNITION
    Publication number: 20240062394
    Abstract: An image recognition system, a sensor module and a method for image recognition are provided. The system includes a processing module, a sensor module, and a database. The sensor module includes first sensors and second sensors, the first sensors are image sensors for object recognition and the second sensors are thermal sensors for human detection. When the image sensors and the thermal sensors are arranged in columns, each column of the image sensors is adjacent to at least one column of the thermal sensors, or when the image sensors and the thermal sensors are arranged in rows, each row of the image sensors is adjacent to at least one row of the thermal sensors, or when the image sensors and the thermal sensors are arranged in a checkerboard manner in the matrix, each of the image sensors is adjacent to the thermal sensors.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: GUO-ZHEN WANG, HAN-CHANG LIN
  • Ion implantation for nano-FET
    Patent number: 11901235
    Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Semiconductor device structure and methods of forming the same
    Patent number: 11901364
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • NETWORK ASSISTANT INFORMATION FOR USER EQUIPMENT TROUBLESHOOTING
    Publication number: 20240048965
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, a network assistant information (NAI) message identifying a set of characteristics of a network connection. The UE may communicate with the network node using a communication configuration associated with the set of characteristics of the network connection. Numerous other aspects are described.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: Kai-Chun CHENG, Jen-Chun CHANG, Kuhn-Chang LIN, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yu-Chieh HUANG, Chun-Hsiang CHIU, ChihHung HSIEH, Chung Wei LIN, Yeong Leong CHOO
  • SUPPORT PLATE, FOLDABLE DISPLAY MODULE, AND FOLDABLE DISPLAY DEVICE
    Publication number: 20240045477
    Abstract: A support plate, including at least one bendable area and a non-bendable area connected to the bendable area. The bendable area includes a first bendable zone and a second bendable zone located between the first bendable zone and the non-bendable area. The first bendable zone includes a first etching pattern, and the second bendable zone includes a second etching pattern. The flexural rigidity of the second bendable zone is greater than the flexural rigidity of the first bendable zone, and is less than the flexural rigidity of the non-bendable area. In the first bendable zone, the closer a region to the second bendable zone, the greater the flexural rigidity of the region.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Applicant: Hefei Visionox Technology Co., Ltd.
    Inventors: Gusheng XU, Guizhou QIAO, Bo YUAN, Chang LIN
  • Spatial quasi-co-location for radio link monitoring in new radio mobile communications
    Patent number: 11895516
    Abstract: Techniques and examples of determination of receiver (RX) beam for radio link monitoring (RLM) based on available spatial quasi-co-location (QCL) information in New Radio (NR) mobile communications are described. An apparatus receives downlink (DL) signaling from a network. The apparatus determines whether to extend an evaluation period of RLM based on a quasi-co-location (QCL) association provided in at least the DL signaling. The apparatus then executes extension of the evaluation period of the RLM, or not, based on a result of the determining.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 6, 2024
    Assignee: MediaTek Inc.
    Inventors: Hsuan-Li Lin, Kuhn-Chang Lin, Tsang-Wei Yu
  • Test kit for testing a device under test
    Patent number: 11879934
    Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 23, 2024
    Assignee: MEDIATEK INC.
    Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Sheng-Wei Lei, Chang-Lin Wei, Chih-Yang Liu, Che-Hsien Huang, Yi-Chieh Lin
  • Apparatus and method for generating an optical signal
    Patent number: 11874538
    Abstract: A directional coupler is configured to receive a continuous light waveform and split the waveform into two carrier signals. Ring modulators are configured to receive the carrier signals and binary data and modulate the carrier signals based on the binary data. A combiner is configured to combine the modulated carrier signals into a four-level pulse amplitude modulation (PAM4) signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Chang Lin, Chan-Hong Chern
  • Wearable device and method for performing registration process in the wearable device
    Patent number: 11864864
    Abstract: A wearable device and a method for performing a registration process in the wearable device are provided. The wearable device includes a light source, a light sensor and a microcontroller that performs the method. In the method, the light source is activated to emit a detection light and the light sensor senses a reflected light. A light intensity of the reflected light is calculated. A registration value is produced based on the light intensity. Specifically, the detection light with a specific frequency to be registered in the registration value is used as a reference to detect whether the wearable device is properly worn by a person. For example, since the wearable device can be worn on the person's wrist, the registration value is used to detect whether the wearable device is away from the wrist.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 9, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chun-Chih Chen, Yung-Chang Lin, Ming-Hsuan Ku
  • CONTACT STRUCTURE FOR STACKED MULTI-GATE DEVICE
    Publication number: 20240006536
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 4, 2024
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Low-loss true time-delay phase shifter
    Patent number: 11862864
    Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 2, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Hsin-Chang Lin
  • Electronic assembly
    Patent number: 11862544
    Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Jen-Chieh Kao
  • Electronic system with eye protection in response to user distance
    Patent number: 11863859
    Abstract: An electronic system including a display device, an image sensor, a face detection engine, an eye detection engine and an eye protection engine is provided. The image sensor captures an image. The face detection engine recognizes a user face in the image. The eye detection engine recognizes user eyes in the image. The eye protection engine turns off the display device when the user eyes are recognized in the image but the user face is not recognized in the image.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: January 2, 2024
    Inventors: Han-Chang Lin, Guo-Zhen Wang, Nien-Tse Chen
  • INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS
    Publication number: 20230420513
    Abstract: An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Transistor Source/Drain Regions and Methods of Forming the Same
    Publication number: 20230420520
    Abstract: In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
    Type: Application
    Filed: January 5, 2023
    Publication date: December 28, 2023
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • METHOD FOR NR RADIO LINK MONITORING (RLM) AND EVALUATION PERIOD DETERMINATION
    Publication number: 20230416132
    Abstract: Methods are proposed to define UE behavior for performing synchronization signal block (SSB) based radio link monitoring (RLM) and channel state information reference signal (CSI-RS) based RLM. In a first novel aspect, if CSI-RS based RLM-RS is not QCLed to any CORESET, then UE determines that CSI-RS RLM configuration is error and does not perform RLM accordingly. In a second novel aspect, SSB for RLM and RLM CSI-RS resources are configured with different numerologies. UE perform SSB based RLM and CSI-RS based RLM based on whether the SSB and CSI-RS resources are TDMed configured by the network. In a third novel aspect, when multiple SMTC configurations are configured to UE, UE determines an SMTC period and whether SMTC and RLM-RS are overlapped for the purpose of RLM evaluation period determination.
    Type: Application
    Filed: July 29, 2023
    Publication date: December 28, 2023
    Inventors: Hsuan-Li Lin, Kuhn-Chang Lin
  • Inner spacers for gate-all-around transistors
    Patent number: 11855216
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Integrated circuits with FinFET gate structures
    Patent number: 11855082
    Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin, Chih-Hao Wang
  • Multi-gate device and related methods
    Patent number: 11854908
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Yi-Ruei Jhan, Kuo-Cheng Chiang, Chih-Hao Wang
  • Image recognition system, sensor module, and method for image recognition
    Patent number: 11854215
    Abstract: An image recognition system includes a processing module, a sensor module, and a database. The sensor module is electrically connected to the processing module. The database is electrically connected to the processing module. The sensor module configured for capturing at least one image. The at least one image is stored in the database. The processing captures a contour of an object from the at least one image and separates the contour of the object into a plurality of portions. A plurality of arrangements is defined between the portions of the contour of the object. The processing module determines a state of the contour of the object based on the arrangements.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 26, 2023
    Assignee: PIXART IMAGING INC.
    Inventors: Guo-Zhen Wang, Han-Chang Lin