Abstract: A method of fabricating a device includes providing a plurality of fins extending from a substrate. In some embodiments, each fin of the plurality of fins includes a plurality of semiconductor channel layers. In various example, the method further includes performing an ion implantation process into a first fin of the plurality of fins to introduce a dopant species into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin. In some embodiments, the ion implantation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin.

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature electrically coupled to the vertical stack of channel members, a silicide layer formed on more than one side of the source/drain feature, and a source/drain contact electrically coupled to the source/drain feature via the silicide layer.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.